38f5bd015f82514d8345e424d6127d86df089c7c
[platform/kernel/u-boot.git] / include / configs / tao3530.h
1 /*
2  * Configuration settings for the TechNexion TAO-3530 SOM
3  * equipped on Thunder baseboard.
4  *
5  * Edward Lin <linuxfae@technexion.com>
6  * Tapani Utriainen <linuxfae@technexion.com>
7  *
8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 /*
17  * High Level Configuration Options
18  */
19
20 #define CONFIG_SDRC                     /* Has an SDRC controller */
21
22 #include <asm/arch/cpu.h>               /* get chip and board defs */
23 #include <asm/arch/omap.h>
24
25 /* Clock Defines */
26 #define V_OSCK                  26000000        /* Clock output from T2 */
27 #define V_SCLK                  (V_OSCK >> 1)
28
29 #define CONFIG_MISC_INIT_R
30
31 #define CONFIG_CMDLINE_TAG
32 #define CONFIG_SETUP_MEMORY_TAGS
33 #define CONFIG_INITRD_TAG
34 #define CONFIG_REVISION_TAG
35
36 /*
37  * Size of malloc() pool
38  */
39 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
40 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
41
42 /*
43  * Hardware drivers
44  */
45
46 /*
47  * NS16550 Configuration
48  */
49 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
50
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
53 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
54
55 /*
56  * select serial console configuration
57  */
58 #define CONFIG_CONS_INDEX               3
59 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
60
61 /* allow to overwrite serial and ethaddr */
62 #define CONFIG_ENV_OVERWRITE
63
64 /* commands to include */
65 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
66 #define MTDIDS_DEFAULT                  "nand0=nand"
67 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
68                                         "1920k(u-boot),128k(u-boot-env),"\
69                                         "4m(kernel),-(fs)"
70
71 #define CONFIG_CMD_NAND         /* NAND support                 */
72
73 #define CONFIG_SYS_I2C
74 #define CONFIG_SYS_I2C_OMAP34XX
75 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
76 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
77 #define CONFIG_I2C_MULTI_BUS
78
79 /*
80  * TWL4030
81  */
82 #define CONFIG_TWL4030_LED
83
84 /*
85  * Board NAND Info.
86  */
87 #define CONFIG_NAND_OMAP_GPMC
88 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
89                                                         /* to access nand */
90 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
91                                                         /* to access nand at */
92                                                         /* CS0 */
93
94 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
95                                                         /* devices */
96 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
97 /* Environment information */
98
99 #define CONFIG_EXTRA_ENV_SETTINGS \
100         "loadaddr=0x82000000\0" \
101         "console=ttyO2,115200n8\0" \
102         "mpurate=600\0" \
103         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
104         "tv_mode=omapfb.mode=tv:ntsc\0" \
105         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
106         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
107         "extra_options= \0" \
108         "mmcdev=0\0" \
109         "mmcroot=/dev/mmcblk0p2 rw\0" \
110         "mmcrootfstype=ext3 rootwait\0" \
111         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
112         "nandrootfstype=ubifs\0" \
113         "mmcargs=setenv bootargs console=${console} " \
114                 "mpurate=${mpurate} " \
115                 "${video_mode} " \
116                 "root=${mmcroot} " \
117                 "rootfstype=${mmcrootfstype} " \
118                 "${extra_options}\0" \
119         "nandargs=setenv bootargs console=${console} " \
120                 "mpurate=${mpurate} " \
121                 "${video_mode} " \
122                 "${network_setting} " \
123                 "root=${nandroot} " \
124                 "rootfstype=${nandrootfstype} "\
125                 "${extra_options}\0" \
126         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
127         "bootscript=echo Running bootscript from mmc ...; " \
128                 "source ${loadaddr}\0" \
129         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
130         "mmcboot=echo Booting from mmc ...; " \
131                 "run mmcargs; " \
132                 "bootm ${loadaddr}\0" \
133         "nandboot=echo Booting from nand ...; " \
134                 "run nandargs; " \
135                 "nand read ${loadaddr} 280000 400000; " \
136                 "bootm ${loadaddr}\0" \
137
138 #define CONFIG_BOOTCOMMAND \
139         "if mmc rescan ${mmcdev}; then " \
140                 "if run loadbootscript; then " \
141                         "run bootscript; " \
142                 "else " \
143                         "if run loaduimage; then " \
144                                 "run mmcboot; " \
145                         "else run nandboot; " \
146                         "fi; " \
147                 "fi; " \
148         "else run nandboot; fi"
149
150 /*
151  * Miscellaneous configurable options
152  */
153 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
154 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
155
156 /* turn on command-line edit/hist/auto */
157 #define CONFIG_CMDLINE_EDITING
158 #define CONFIG_AUTO_COMPLETE
159
160 /* Print Buffer Size */
161 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
162                                         sizeof(CONFIG_SYS_PROMPT) + 16)
163 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
164 /* Boot Argument Buffer Size */
165 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
166
167 #define CONFIG_SYS_ALT_MEMTEST          1
168 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
169                                                                 /* defaults */
170 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
171 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
172
173 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
174                                                         /* load address */
175 #define CONFIG_SYS_TEXT_BASE            0x80008000
176
177 /*
178  * OMAP3 has 12 GP timers, they can be driven by the system clock
179  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
180  * This rate is divided by a local divisor.
181  */
182 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
183 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
184
185 /*
186  * Physical Memory Map
187  */
188 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
189 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
190 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
191 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
192
193 /*
194  * FLASH and environment organization
195  */
196
197 /* **** PISMO SUPPORT *** */
198 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
199 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
200
201 /* Monitor at start of flash */
202 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
203 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
204
205 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
206 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
207
208 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
209 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
210 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
211
212 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
213 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
214 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
215 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
216                                          CONFIG_SYS_INIT_RAM_SIZE - \
217                                          GENERATED_GBL_DATA_SIZE)
218
219 #define CONFIG_OMAP3_SPI
220
221 /*
222  * USB
223  *
224  * Currently only EHCI is enabled, the MUSB OTG controller
225  * is not enabled.
226  */
227
228 /* USB EHCI */
229 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
230
231 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
232 #define CONFIG_USB_HOST_ETHER
233 #define CONFIG_USB_ETHER_SMSC95XX
234
235 #define CONFIG_USB_ETHER
236 #define CONFIG_USB_ETHER_RNDIS
237
238 /* Defines for SPL */
239 #define CONFIG_SPL_FRAMEWORK
240 #define CONFIG_SPL_NAND_SIMPLE
241
242 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
243 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
244
245 #define CONFIG_SPL_NAND_BASE
246 #define CONFIG_SPL_NAND_DRIVERS
247 #define CONFIG_SPL_NAND_ECC
248 #define CONFIG_SPL_OMAP3_ID_NAND
249 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
250
251 /* NAND boot config */
252 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
253 #define CONFIG_SYS_NAND_PAGE_COUNT      64
254 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
255 #define CONFIG_SYS_NAND_OOBSIZE         64
256 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
257 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
258 /*
259  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
260  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
261  */
262 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
263                                          10, 11, 12, 13 }
264 #define CONFIG_SYS_NAND_ECCSIZE         512
265 #define CONFIG_SYS_NAND_ECCBYTES        3
266 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
267
268 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
269 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
270
271 #define CONFIG_SPL_TEXT_BASE            0x40200800
272 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
273                                          CONFIG_SPL_TEXT_BASE)
274
275 /*
276  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
277  * older x-loader implementations. And move the BSS area so that it
278  * doesn't overlap with TEXT_BASE.
279  */
280 #define CONFIG_SYS_TEXT_BASE            0x80008000
281 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
282 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
283
284 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
285 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
286
287 #endif /* __CONFIG_H */