include/configs/tao3530.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuration settings for the TechNexion TAO-3530 SOM
   4  * equipped on Thunder baseboard.
   5  *
   6  * Edward Lin <linuxfae@technexion.com>
   7  * Tapani Utriainen <linuxfae@technexion.com>
   8  *
   9  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #include <asm/arch/cpu.h>               /* get chip and board defs */
  20 #include <asm/arch/omap.h>
  21
  22 /* Clock Defines */
  23 #define V_OSCK                  26000000        /* Clock output from T2 */
  24 #define V_SCLK                  (V_OSCK >> 1)
  25
  26 #define CONFIG_MISC_INIT_R
  27
  28 #define CONFIG_CMDLINE_TAG
  29 #define CONFIG_SETUP_MEMORY_TAGS
  30 #define CONFIG_INITRD_TAG
  31 #define CONFIG_REVISION_TAG
  32
  33 /*
  34  * Size of malloc() pool
  35  */
  36 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  37 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  38
  39 /*
  40  * Hardware drivers
  41  */
  42
  43 /*
  44  * NS16550 Configuration
  45  */
  46 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  47
  48 #define CONFIG_SYS_NS16550_SERIAL
  49 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  50 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  51
  52 /*
  53  * select serial console configuration
  54  */
  55 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  56
  57 /* allow to overwrite serial and ethaddr */
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 /* commands to include */
  61 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  62
  63 #define CONFIG_SYS_I2C
  64 #define CONFIG_I2C_MULTI_BUS
  65
  66 /*
  67  * TWL4030
  68  */
  69 #define CONFIG_TWL4030_LED
  70
  71 /*
  72  * Board NAND Info.
  73  */
  74 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  75                                                         /* to access nand */
  76 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  77                                                         /* to access nand at */
  78                                                         /* CS0 */
  79
  80 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  81                                                         /* devices */
  82 /* Environment information */
  83
  84 #define CONFIG_EXTRA_ENV_SETTINGS \
  85         "loadaddr=0x82000000\0" \
  86         "console=ttyO2,115200n8\0" \
  87         "mpurate=600\0" \
  88         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
  89         "tv_mode=omapfb.mode=tv:ntsc\0" \
  90         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
  91         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
  92         "extra_options= \0" \
  93         "mmcdev=0\0" \
  94         "mmcroot=/dev/mmcblk0p2 rw\0" \
  95         "mmcrootfstype=ext3 rootwait\0" \
  96         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
  97         "nandrootfstype=ubifs\0" \
  98         "mmcargs=setenv bootargs console=${console} " \
  99                 "mpurate=${mpurate} " \
 100                 "${video_mode} " \
 101                 "root=${mmcroot} " \
 102                 "rootfstype=${mmcrootfstype} " \
 103                 "${extra_options}\0" \
 104         "nandargs=setenv bootargs console=${console} " \
 105                 "mpurate=${mpurate} " \
 106                 "${video_mode} " \
 107                 "${network_setting} " \
 108                 "root=${nandroot} " \
 109                 "rootfstype=${nandrootfstype} "\
 110                 "${extra_options}\0" \
 111         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 112         "bootscript=echo Running bootscript from mmc ...; " \
 113                 "source ${loadaddr}\0" \
 114         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 115         "mmcboot=echo Booting from mmc ...; " \
 116                 "run mmcargs; " \
 117                 "bootm ${loadaddr}\0" \
 118         "nandboot=echo Booting from nand ...; " \
 119                 "run nandargs; " \
 120                 "nand read ${loadaddr} 280000 400000; " \
 121                 "bootm ${loadaddr}\0" \
 122
 123 #define CONFIG_BOOTCOMMAND \
 124         "if mmc rescan ${mmcdev}; then " \
 125                 "if run loadbootscript; then " \
 126                         "run bootscript; " \
 127                 "else " \
 128                         "if run loaduimage; then " \
 129                                 "run mmcboot; " \
 130                         "else run nandboot; " \
 131                         "fi; " \
 132                 "fi; " \
 133         "else run nandboot; fi"
 134
 135 /*
 136  * Miscellaneous configurable options
 137  */
 138
 139 /* turn on command-line edit/hist/auto */
 140
 141 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 142                                                                 /* defaults */
 143 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 144 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 145
 146 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 147                                                         /* load address */
 148
 149 /*
 150  * OMAP3 has 12 GP timers, they can be driven by the system clock
 151  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 152  * This rate is divided by a local divisor.
 153  */
 154 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 155 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 156
 157 /*
 158  * Physical Memory Map
 159  */
 160 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 161 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 162 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 163 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 164
 165 /*
 166  * FLASH and environment organization
 167  */
 168
 169 /* **** PISMO SUPPORT *** */
 170 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 171 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 172
 173 /* Monitor at start of flash */
 174 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 175 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 176
 177 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 178
 179 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 180 #define CONFIG_ENV_OFFSET               0x260000
 181 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 182
 183 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 184 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 185 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 186 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 187                                          CONFIG_SYS_INIT_RAM_SIZE - \
 188                                          GENERATED_GBL_DATA_SIZE)
 189
 190 /*
 191  * USB
 192  *
 193  * Currently only EHCI is enabled, the MUSB OTG controller
 194  * is not enabled.
 195  */
 196
 197 /* USB EHCI */
 198 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 199
 200 /* Defines for SPL */
 201
 202 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 203 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 204
 205 #define CONFIG_SPL_NAND_BASE
 206 #define CONFIG_SPL_NAND_DRIVERS
 207 #define CONFIG_SPL_NAND_ECC
 208
 209 /* NAND boot config */
 210 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 211 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 212 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 213 #define CONFIG_SYS_NAND_OOBSIZE         64
 214 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 215 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 216 /*
 217  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 218  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 219  */
 220 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 221                                          10, 11, 12, 13 }
 222 #define CONFIG_SYS_NAND_ECCSIZE         512
 223 #define CONFIG_SYS_NAND_ECCBYTES        3
 224 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 225
 226 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 228
 229 #define CONFIG_SPL_TEXT_BASE            0x40200800
 230 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 231                                          CONFIG_SPL_TEXT_BASE)
 232
 233 /*
 234  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 235  * older x-loader implementations. And move the BSS area so that it
 236  * doesn't overlap with TEXT_BASE.
 237  */
 238 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 239 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 240
 241 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 242 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 243
 244 #endif /* __CONFIG_H */