Merge 'u-boot-imx/master' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / taishan.h
1 /*
2  * (C) Copyright 2007
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /************************************************************************
9  * TAISHAN.h - configuration for AMCC 440GX Ref
10  ***********************************************************************/
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*-----------------------------------------------------------------------
16  * High Level Configuration Options
17  *----------------------------------------------------------------------*/
18 #define CONFIG_TAISHAN          1       /* Board is taishan             */
19 #define CONFIG_440GX            1       /* Specifc GX support           */
20 #define CONFIG_440              1       /* ... PPC440 family            */
21 #define CONFIG_4xx              1       /* ... PPC4xx family            */
22 #define CONFIG_SYS_CLK_FREQ     33333333 /* external freq to pll        */
23
24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
25
26 /*
27  * Include common defines/options for all AMCC eval boards
28  */
29 #define CONFIG_HOSTNAME         taishan
30 #define CONFIG_USE_TTY          ttyS1
31 #include "amcc-common.h"
32
33 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
34 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
35
36 /*-----------------------------------------------------------------------
37  * Base addresses -- Note these are effective addresses where the
38  * actual resources get mapped (not physical addresses)
39  *----------------------------------------------------------------------*/
40 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
41 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
42 #define CONFIG_SYS_ISRAM_BASE           0xc0000000      /* internal SRAM        */
43 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
44
45 #define CONFIG_SYS_EBC0_FLASH_BASE      CONFIG_SYS_FLASH_BASE
46 #define CONFIG_SYS_EBC1_FPGA_BASE       (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
47 #define CONFIG_SYS_EBC2_LCM_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
48 #define CONFIG_SYS_EBC3_CONN_BASE       (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
49
50 #define CONFIG_SYS_GPIO_BASE            (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
51
52 /*-----------------------------------------------------------------------
53  * Initial RAM & stack pointer (placed in internal SRAM)
54  *----------------------------------------------------------------------*/
55 #define CONFIG_SYS_TEMP_STACK_OCM       1
56 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
57 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE  /* Initial RAM address   */
58 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM*/
59
60 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
61 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
62
63 /*-----------------------------------------------------------------------
64  * Serial Port
65  *----------------------------------------------------------------------*/
66 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
67 #define CONFIG_SYS_EXT_SERIAL_CLOCK     (1843200 * 6)   /* Ext clk @ 11.059 MHz */
68
69 /*-----------------------------------------------------------------------
70  * Environment
71  *----------------------------------------------------------------------*/
72 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
73
74 /*-----------------------------------------------------------------------
75  * FLASH related
76  *----------------------------------------------------------------------*/
77 #define CONFIG_SYS_FLASH_CFI
78 #define CONFIG_FLASH_CFI_DRIVER
79 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
81
82 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
83 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
84 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
85
86 #undef  CONFIG_SYS_FLASH_CHECKSUM
87 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
88 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
89
90 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
91 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
92 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
93
94 /* Address and size of Redundant Environment Sector     */
95 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
96 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
97
98 /*-----------------------------------------------------------------------
99  * E2PROM bootstrap configure value
100  *----------------------------------------------------------------------*/
101
102 /*
103  * 800/133/66
104  * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
105  */
106
107 /*
108  * 800/160/80
109  * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
110  */
111
112 /*-----------------------------------------------------------------------
113  * DDR SDRAM
114  *----------------------------------------------------------------------*/
115 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
116 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
117 #define CONFIG_SYS_SDRAM0_TR0           0xC10A401A
118 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
119
120 /*-----------------------------------------------------------------------
121  * I2C
122  *----------------------------------------------------------------------*/
123 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
124
125 #undef CONFIG_SYS_I2C_MULTI_EEPROMS
126 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
127 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
130
131 #define CONFIG_SYS_BOOTSTRAP_IIC_ADDR   0x50
132
133 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
134 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
135 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
136 #define CONFIG_SYS_DTT_MAX_TEMP 70
137 #define CONFIG_SYS_DTT_LOW_TEMP -30
138 #define CONFIG_SYS_DTT_HYSTERESIS       3
139
140 /*
141  * Default environment variables
142  */
143 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
144         CONFIG_AMCC_DEF_ENV                                             \
145         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
146         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
147         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
148         "kernel_addr=fc000000\0"                                        \
149         "ramdisk_addr=fc180000\0"                                       \
150         "kozio=bootm 0xffe00000\0"                                      \
151         ""
152
153 /*-----------------------------------------------------------------------
154  * Networking
155  *----------------------------------------------------------------------*/
156 #define CONFIG_EMAC_NR_START    2       /* start with EMAC 2 (skip 0&1) */
157 #define CONFIG_PHY_ADDR         0xff         /* no phy on EMAC0         */
158 #define CONFIG_PHY1_ADDR        0xff         /* no phy on EMAC1         */
159 #define CONFIG_PHY2_ADDR        0x1
160 #define CONFIG_PHY3_ADDR        0x3
161 #define CONFIG_ET1011C_PHY      1
162 #define CONFIG_HAS_ETH0
163 #define CONFIG_HAS_ETH1
164 #define CONFIG_HAS_ETH2
165 #define CONFIG_HAS_ETH3
166 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
167 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
168 #define CONFIG_PHY_RESET_DELAY  1000
169
170 /*
171  * Commands additional to the ones defined in amcc-common.h
172  */
173 #define CONFIG_CMD_DTT
174 #define CONFIG_CMD_PCI
175
176 /*-----------------------------------------------------------------------
177  * PCI stuff
178  *-----------------------------------------------------------------------
179  */
180 /* General PCI */
181 #define CONFIG_PCI                      /* include pci support          */
182 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
183 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
184 #define CONFIG_EEPRO100       1         /* include PCI EEPRO100         */
185 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
186 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
187
188 /* Board-specific PCI */
189 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
190
191 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
192 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
193
194 #endif  /* __CONFIG_H */