3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 /************************************************************************
22 * TAISHAN.h - configuration for AMCC 440GX Ref
23 ***********************************************************************/
28 /*-----------------------------------------------------------------------
29 * High Level Configuration Options
30 *----------------------------------------------------------------------*/
31 #define CONFIG_TAISHAN 1 /* Board is taishan */
32 #define CONFIG_440GX 1 /* Specifc GX support */
33 #define CONFIG_440 1 /* ... PPC440 family */
34 #define CONFIG_4xx 1 /* ... PPC4xx family */
35 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
38 * Include common defines/options for all AMCC eval boards
40 #define CONFIG_HOSTNAME taishan
41 #define CONFIG_USE_TTY ttyS1
42 #include "amcc-common.h"
44 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
45 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
47 /*-----------------------------------------------------------------------
48 * Base addresses -- Note these are effective addresses where the
49 * actual resources get mapped (not physical addresses)
50 *----------------------------------------------------------------------*/
51 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
52 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
53 #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
54 #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
55 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
57 #define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE
58 #define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000)
59 #define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000)
60 #define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000)
62 #define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
64 /*-----------------------------------------------------------------------
65 * Initial RAM & stack pointer (placed in internal SRAM)
66 *----------------------------------------------------------------------*/
67 #define CFG_TEMP_STACK_OCM 1
68 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
69 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
70 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/
71 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
73 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
74 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
75 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
77 /*-----------------------------------------------------------------------
79 *----------------------------------------------------------------------*/
80 #define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */
81 #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
83 /*-----------------------------------------------------------------------
85 *----------------------------------------------------------------------*/
86 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
88 /*-----------------------------------------------------------------------
90 *----------------------------------------------------------------------*/
92 #define CONFIG_FLASH_CFI_DRIVER
93 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
94 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
96 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
97 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
98 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
100 #undef CFG_FLASH_CHECKSUM
101 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
102 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
104 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
105 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
106 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
108 /* Address and size of Redundant Environment Sector */
109 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
112 /*-----------------------------------------------------------------------
113 * E2PROM bootstrap configure value
114 *----------------------------------------------------------------------*/
118 * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
123 * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
126 /*-----------------------------------------------------------------------
128 *----------------------------------------------------------------------*/
129 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
130 #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
131 #define CFG_SDRAM0_TR0 0xC10A401A
132 #undef CONFIG_SDRAM_ECC /* enable ECC support */
134 /*-----------------------------------------------------------------------
136 *----------------------------------------------------------------------*/
137 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
139 #undef CFG_I2C_MULTI_EEPROMS
140 #define CFG_I2C_EEPROM_ADDR 0x50
141 #define CFG_I2C_EEPROM_ADDR_LEN 1
142 #define CFG_EEPROM_PAGE_WRITE_ENABLE
143 #define CFG_EEPROM_PAGE_WRITE_BITS 3
144 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
146 #define CFG_BOOTSTRAP_IIC_ADDR 0x50
148 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
149 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
150 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
151 #define CFG_DTT_MAX_TEMP 70
152 #define CFG_DTT_LOW_TEMP -30
153 #define CFG_DTT_HYSTERESIS 3
156 * Default environment variables
158 #define CONFIG_EXTRA_ENV_SETTINGS \
159 CONFIG_AMCC_DEF_ENV \
160 CONFIG_AMCC_DEF_ENV_POWERPC \
161 CONFIG_AMCC_DEF_ENV_PPC_OLD \
162 CONFIG_AMCC_DEF_ENV_NOR_UPD \
163 "kernel_addr=fc000000\0" \
164 "ramdisk_addr=fc180000\0" \
165 "kozio=bootm 0xffe00000\0" \
168 /*-----------------------------------------------------------------------
170 *----------------------------------------------------------------------*/
171 #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
172 #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
173 #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
174 #define CONFIG_PHY2_ADDR 0x1
175 #define CONFIG_PHY3_ADDR 0x3
176 #define CONFIG_ET1011C_PHY 1
177 #define CONFIG_HAS_ETH0
178 #define CONFIG_HAS_ETH1
179 #define CONFIG_HAS_ETH2
180 #define CONFIG_HAS_ETH3
181 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
182 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
183 #define CONFIG_PHY_RESET_DELAY 1000
186 * Commands additional to the ones defined in amcc-common.h
188 #define CONFIG_CMD_DTT
189 #define CONFIG_CMD_PCI
191 /*-----------------------------------------------------------------------
193 *-----------------------------------------------------------------------
196 #define CONFIG_PCI /* include pci support */
197 #define CONFIG_PCI_PNP /* do pci plug-and-play */
198 #define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
199 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
200 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
202 /* Board-specific PCI */
203 #define CFG_PCI_TARGET_INIT /* let board init pci target */
205 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
206 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
208 #endif /* __CONFIG_H */