include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "suvd3"
  24 #define CONFIG_KM_BOARD_NAME   "suvd3"
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE       /* Has QE */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all Keymile boards */
  35 #include "km/keymile-common.h"
  36 #include "km/km-powerpc.h"
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * IMMR new address
  47  */
  48 #define CONFIG_SYS_IMMR         0xE0000000
  49
  50 /*
  51  * Bus Arbitration Configuration Register (ACR)
  52  */
  53 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  54 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  55 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  56 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  63 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  64
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  67                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  68
  69 #define CFG_83XX_DDR_USES_CS0
  70
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_DDR_II
  75 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  76
  77 /*
  78  * The reserved memory
  79  */
  80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  81 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  82
  83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_SYS_RAMBOOT
  85 #endif
  86
  87 /* Reserve 768 kB for Mon */
  88 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  89
  90 /*
  91  * Initial RAM Base Address Setup
  92  */
  93 #define CONFIG_SYS_INIT_RAM_LOCK
  94 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  95 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  96 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  97                                                 GENERATED_GBL_DATA_SIZE)
  98
  99 /*
 100  * Init Local Bus Memory Controller:
 101  *
 102  * Bank Bus     Machine PortSz  Size  Device
 103  * ---- ---     ------- ------  -----  ------
 104  *  0   Local   GPCM    16 bit  256MB FLASH
 105  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 106  *
 107  */
 108 /*
 109  * FLASH on the Local Bus
 110  */
 111 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 112
 113 /* FLASH */
 114 #define CONFIG_SYS_BR0_PRELIM   (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 115 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 116
 117 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 118 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 119 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 120
 121 /*
 122  * PRIO1/PIGGY on the local bus CS1
 123  */
 124
 125 /* KMBEC_FPGA */
 126 #define CONFIG_SYS_BR1_PRELIM   (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 127 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 128
 129 /*
 130  * Serial Port
 131  */
 132 #define CONFIG_SYS_NS16550_SERIAL
 133 #define CONFIG_SYS_NS16550_REG_SIZE     1
 134 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 135
 136 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 137 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 138
 139 /*
 140  * QE UEC ethernet configuration
 141  */
 142 #define CONFIG_UEC_ETH
 143 #define CONFIG_ETHPRIME         "UEC0"
 144
 145 #define CONFIG_UEC_ETH1         /* GETH1 */
 146 #define UEC_VERBOSE_DEBUG       1
 147
 148 #ifdef CONFIG_UEC_ETH1
 149 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 150 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 151 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 152 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 153 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 154 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 155 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 156 #endif
 157
 158 /*
 159  * Environment
 160  */
 161
 162 #ifndef CONFIG_SYS_RAMBOOT
 163 #ifndef CONFIG_ENV_ADDR
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 165                                         CONFIG_SYS_MONITOR_LEN)
 166 #endif
 167 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 168 #ifndef CONFIG_ENV_OFFSET
 169 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 170 #endif
 171
 172 /* Address and size of Redundant Environment Sector     */
 173 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 174                                                 CONFIG_ENV_SECT_SIZE)
 175 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 176
 177 #else /* CFG_SYS_RAMBOOT */
 178 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 179 #define CONFIG_ENV_SIZE         0x2000
 180 #endif /* CFG_SYS_RAMBOOT */
 181
 182 /* I2C */
 183 #define CONFIG_SYS_I2C
 184 #define CONFIG_SYS_NUM_I2C_BUSES        4
 185 #define CONFIG_SYS_I2C_MAX_HOPS         1
 186 #define CONFIG_SYS_I2C_FSL
 187 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 188 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 189 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 190 #define CONFIG_SYS_I2C_OFFSET           0x3000
 191 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 192 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 193 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 194 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 195                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 196                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 197                 {1, {I2C_NULL_HOP} } }
 198
 199 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 200
 201 #if defined(CONFIG_CMD_NAND)
 202 #define CONFIG_NAND_KMETER1
 203 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 204 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 205 #endif
 206
 207 /*
 208  * For booting Linux, the board info and command line data
 209  * have to be in the first 8 MB of memory, since this is
 210  * the maximum mapped by the Linux kernel during initialization.
 211  */
 212 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 213
 214 /*
 215  * Core HID Setup
 216  */
 217 #define CONFIG_SYS_HID0_INIT            0x000000000
 218 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 219                                          HID0_ENABLE_INSTRUCTION_CACHE)
 220 #define CONFIG_SYS_HID2                 HID2_HBE
 221
 222 /*
 223  * Internal Definitions
 224  */
 225 #define BOOTFLASH_START 0xF0000000
 226
 227 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 228
 229 /*
 230  * Environment Configuration
 231  */
 232 #define CONFIG_ENV_OVERWRITE
 233 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 234 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 235 #endif
 236
 237 #ifndef CONFIG_KM_DEF_ARCH
 238 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 239 #endif
 240
 241 #define CONFIG_EXTRA_ENV_SETTINGS \
 242         CONFIG_KM_DEF_ENV                                               \
 243         CONFIG_KM_DEF_ARCH                                              \
 244         "newenv="                                                       \
 245                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 246                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 247         "unlock=yes\0"                                                  \
 248         ""
 249
 250 #if defined(CONFIG_UEC_ETH)
 251 #define CONFIG_HAS_ETH0
 252 #endif
 253
 254 /*
 255  * System IO Config
 256  */
 257 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 258
 259 #define CONFIG_SYS_DDRCDR (\
 260         DDRCDR_EN | \
 261         DDRCDR_PZ_MAXZ | \
 262         DDRCDR_NZ_MAXZ | \
 263         DDRCDR_M_ODR)
 264
 265 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 266 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 267                                          SDRAM_CFG_32_BE | \
 268                                          SDRAM_CFG_SREN | \
 269                                          SDRAM_CFG_HSE)
 270
 271 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 272 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 273 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 274                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 275
 276 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 277                                          CSCONFIG_ODT_WR_CFG | \
 278                                          CSCONFIG_ROW_BIT_13 | \
 279                                          CSCONFIG_COL_BIT_10)
 280
 281 #define CONFIG_SYS_DDR_MODE     0x47860242
 282 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 283
 284 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 285                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 286                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 287                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 288                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 289                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 290                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 291                                  (0 << TIMING_CFG0_RWT_SHIFT))
 292
 293 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 294                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 295                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 296                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 297                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 298                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 299                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 300                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 301
 302 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 303                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 304                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 305                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 306                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 307                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 308                                  (5 << TIMING_CFG2_CPO_SHIFT))
 309
 310 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 311
 312 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 313 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 314
 315 /* EEprom support */
 316 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 317
 318 /*
 319  * Local Bus Configuration & Clock Setup
 320  */
 321 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 322 #define CONFIG_SYS_LCRR_EADC    0x00010000
 323 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 324
 325 #define CONFIG_SYS_LBC_LBCR     0x00000000
 326
 327 #define CONFIG_SYS_APP1_BASE            0xA0000000
 328 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 329 #define CONFIG_SYS_APP2_BASE            0xB0000000
 330 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 331
 332 /* EEprom support */
 333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 334
 335 /*
 336  * Init Local Bus Memory Controller:
 337  *
 338  * Bank Bus     Machine PortSz  Size  Device
 339  * ---- ---     ------- ------  -----  ------
 340  *  2   Local   UPMA    16 bit  256MB APP1
 341  *  3   Local   GPCM    16 bit  256MB APP2
 342  *
 343  */
 344
 345 /* APP1 */
 346 #define CONFIG_SYS_BR2_PRELIM   (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
 347 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256MB)
 348
 349 /* APP2 */
 350 #define CONFIG_SYS_BR3_PRELIM   (0xB0000000 | BR_PS_16 | BR_V)
 351 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
 352
 353 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 354                          0x0000c000 | \
 355                          MxMR_WLFx_2X)
 356 #endif /* __CONFIG_H */