include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME         "suvd3"
  26 #define CONFIG_KM_BOARD_NAME   "suvd3"
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_QE       /* Has QE */
  32 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  33
  34 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  35
  36 /* include common defines/options for all 83xx Keymile boards */
  37 #include "km83xx-common.h"
  38
  39 /*
  40  * System IO Config
  41  */
  42 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  43
  44 /*
  45  * Hardware Reset Configuration Word
  46  */
  47 #define CONFIG_SYS_HRCW_LOW (\
  48         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  49         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  50         HRCWL_CSB_TO_CLKIN_2X1 | \
  51         HRCWL_CORE_TO_CSB_2_5X1 | \
  52         HRCWL_CE_PLL_VCO_DIV_2 | \
  53         HRCWL_CE_TO_PLL_1X3)
  54
  55 #define CONFIG_SYS_HRCW_HIGH (\
  56         HRCWH_PCI_AGENT | \
  57         HRCWH_PCI_ARBITER_DISABLE | \
  58         HRCWH_CORE_ENABLE | \
  59         HRCWH_FROM_0X00000100 | \
  60         HRCWH_BOOTSEQ_DISABLE | \
  61         HRCWH_SW_WATCHDOG_DISABLE | \
  62         HRCWH_ROM_LOC_LOCAL_16BIT | \
  63         HRCWH_BIG_ENDIAN | \
  64         HRCWH_LALE_NORMAL)
  65
  66 #define CONFIG_SYS_DDRCDR (\
  67         DDRCDR_EN | \
  68         DDRCDR_PZ_MAXZ | \
  69         DDRCDR_NZ_MAXZ | \
  70         DDRCDR_M_ODR)
  71
  72 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  73 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  74                                          SDRAM_CFG_32_BE | \
  75                                          SDRAM_CFG_SREN | \
  76                                          SDRAM_CFG_HSE)
  77
  78 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  79 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  80 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  81                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  82
  83 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  84                                          CSCONFIG_ODT_WR_CFG | \
  85                                          CSCONFIG_ROW_BIT_13 | \
  86                                          CSCONFIG_COL_BIT_10)
  87
  88 #define CONFIG_SYS_DDR_MODE     0x47860242
  89 #define CONFIG_SYS_DDR_MODE2    0x8080c000
  90
  91 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  92                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  93                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  94                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  95                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  96                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  97                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  98                                  (0 << TIMING_CFG0_RWT_SHIFT))
  99
 100 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 101                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 102                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 103                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 104                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 105                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 106                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 107                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 108
 109 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 110                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 111                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 112                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 113                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 114                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 115                                  (5 << TIMING_CFG2_CPO_SHIFT))
 116
 117 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 118
 119 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 120 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 121
 122 /* EEprom support */
 123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 124
 125 /*
 126  * Local Bus Configuration & Clock Setup
 127  */
 128 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 129 #define CONFIG_SYS_LCRR_EADC    0x00010000
 130 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 131
 132 #define CONFIG_SYS_LBC_LBCR     0x00000000
 133
 134 /*
 135  * MMU Setup
 136  */
 137 #define CONFIG_SYS_IBAT7L       (0)
 138 #define CONFIG_SYS_IBAT7U       (0)
 139 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 140 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 141
 142 #define CONFIG_SYS_APP1_BASE            0xA0000000
 143 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 144 #define CONFIG_SYS_APP2_BASE            0xB0000000
 145 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 146
 147 /* EEprom support */
 148 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 149
 150 /*
 151  * Init Local Bus Memory Controller:
 152  *
 153  * Bank Bus     Machine PortSz  Size  Device
 154  * ---- ---     ------- ------  -----  ------
 155  *  2   Local   UPMA    16 bit  256MB APP1
 156  *  3   Local   GPCM    16 bit  256MB APP2
 157  *
 158  */
 159
 160 /*
 161  * APP1 on the local bus CS2
 162  */
 163 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 164 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 165
 166 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 167                                  BR_PS_16 | \
 168                                  BR_MS_UPMA | \
 169                                  BR_V)
 170 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 171
 172 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 173                                  BR_PS_16 | \
 174                                  BR_V)
 175
 176 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 177                                  OR_GPCM_CSNT | \
 178                                  OR_GPCM_ACS_DIV4 | \
 179                                  OR_GPCM_SCY_3 | \
 180                                  OR_GPCM_TRLX_SET)
 181
 182 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 183                          0x0000c000 | \
 184                          MxMR_WLFx_2X)
 185
 186 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 187 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 188
 189 /*
 190  * MMU Setup
 191  */
 192 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
 193 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 194                                  BATL_MEMCOHERENCE)
 195 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 196                                  BATU_VS | BATU_VP)
 197 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 198                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 199 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 200 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 201                                  BATL_MEMCOHERENCE)
 202 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 203                                  BATU_VS | BATU_VP)
 204 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 205                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 206 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 207
 208 #endif /* __CONFIG_H */