include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 /* This needs to be set prior to including km/km83xx-common.h */
  24
  25 #define CONFIG_HOSTNAME         "suvd3"
  26 #define CONFIG_KM_BOARD_NAME   "suvd3"
  27 /* include common defines/options for all 8321 Keymile boards */
  28 #include "km/km8321-common.h"
  29
  30 #define CONFIG_SYS_APP1_BASE            0xA0000000
  31 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
  32 #define CONFIG_SYS_APP2_BASE            0xB0000000
  33 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
  34
  35 /* EEprom support */
  36 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  37
  38 /*
  39  * Init Local Bus Memory Controller:
  40  *
  41  * Bank Bus     Machine PortSz  Size  Device
  42  * ---- ---     ------- ------  -----  ------
  43  *  2   Local   UPMA    16 bit  256MB APP1
  44  *  3   Local   GPCM    16 bit  256MB APP2
  45  *
  46  */
  47
  48 /*
  49  * APP1 on the local bus CS2
  50  */
  51 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
  52 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  53
  54 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
  55                                  BR_PS_16 | \
  56                                  BR_MS_UPMA | \
  57                                  BR_V)
  58 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
  59
  60 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
  61                                  BR_PS_16 | \
  62                                  BR_V)
  63
  64 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
  65                                  OR_GPCM_CSNT | \
  66                                  OR_GPCM_ACS_DIV4 | \
  67                                  OR_GPCM_SCY_3 | \
  68                                  OR_GPCM_TRLX_SET)
  69
  70 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
  71                          0x0000c000 | \
  72                          MxMR_WLFx_2X)
  73
  74 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
  75 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  76
  77 /*
  78  * MMU Setup
  79  */
  80 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
  81 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
  82                                  BATL_MEMCOHERENCE)
  83 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
  84                                  BATU_VS | BATU_VP)
  85 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
  86                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  87 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
  88 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  89                                  BATL_MEMCOHERENCE)
  90 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
  91                                  BATU_VS | BATU_VP)
  92 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
  93                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  94 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
  95
  96 #endif /* __CONFIG_H */