2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
26 * U-Boot port on STx XTc 8xx board
27 * Mostly copied from Panto's NETTA2 board.
34 * High Level Configuration Options
38 #define CONFIG_MPC875 1 /* This is a MPC875 CPU */
39 #define CONFIG_STXXTC 1 /* ...on a STx XTc board */
41 #define CONFIG_SYS_TEXT_BASE 0x40F00000
43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44 #undef CONFIG_8xx_CONS_SMC2
45 #undef CONFIG_8xx_CONS_NONE
47 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
49 #define CONFIG_XIN 10000000 /* 10 MHz input xtal */
51 /* Select one of few clock rates defined later in this file.
53 /* #define MPC8XX_HZ 50000000 */
54 #define MPC8XX_HZ 66666666
56 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
59 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
61 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
66 #undef CONFIG_BOOTARGS
67 #define CONFIG_BOOTCOMMAND \
69 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
74 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
75 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
77 #undef CONFIG_WATCHDOG /* watchdog disabled */
79 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
80 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
85 #define CONFIG_BOOTP_SUBNETMASK
86 #define CONFIG_BOOTP_GATEWAY
87 #define CONFIG_BOOTP_HOSTNAME
88 #define CONFIG_BOOTP_BOOTPATH
89 #define CONFIG_BOOTP_BOOTFILESIZE
90 #define CONFIG_BOOTP_NISDOMAIN
93 #undef CONFIG_MAC_PARTITION
94 #undef CONFIG_DOS_PARTITION
96 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
98 #define FEC_ENET 1 /* eth.c needs it that way... */
99 #undef CONFIG_SYS_DISCOVER_PHY
101 #define CONFIG_MII_INIT 1
104 #define CONFIG_ETHER_ON_FEC1 1
105 #define CONFIG_FEC1_PHY 1 /* phy address of FEC */
106 #undef CONFIG_FEC1_PHY_NORXERR
108 #define CONFIG_ETHER_ON_FEC2 1
109 #define CONFIG_FEC2_PHY 3
110 #undef CONFIG_FEC2_PHY_NORXERR
112 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
116 * Command line configuration.
118 #include <config_cmd_default.h>
120 #define CONFIG_CMD_DHCP
121 #define CONFIG_CMD_MII
122 #define CONFIG_CMD_NFS
123 #define CONFIG_CMD_PING
126 #define CONFIG_BOARD_EARLY_INIT_F 1
127 #define CONFIG_MISC_INIT_R
130 * Miscellaneous configurable options
132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
133 #define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
135 #define CONFIG_SYS_HUSH_PARSER 1
136 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138 #if defined(CONFIG_CMD_KGDB)
139 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
141 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
143 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
148 #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
150 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
152 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
155 * Low Level Configuration Settings
156 * (address mappings, register initial values, etc.)
157 * You should know what you are doing if you make changes here.
159 /*-----------------------------------------------------------------------
160 * Internal Memory Mapped Register
162 #define CONFIG_SYS_IMMR 0xFF000000
164 /*-----------------------------------------------------------------------
165 * Definitions for initial stack pointer and data area (in DPRAM)
167 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
168 #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
172 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
177 #define CONFIG_SYS_SDRAM_BASE 0x00000000
178 #define CONFIG_SYS_FLASH_BASE 0x40000000
180 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
182 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
185 /* yes this is weird, I know :) */
186 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
187 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 #define CONFIG_SYS_RESET_ADDRESS 0x80000000
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
196 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
198 /*-----------------------------------------------------------------------
201 #define CONFIG_ENV_IS_IN_FLASH 1
202 #define CONFIG_ENV_SECT_SIZE 0x10000
204 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
205 #define CONFIG_ENV_OFFSET 0
206 #define CONFIG_ENV_SIZE 0x4000
208 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
209 #define CONFIG_ENV_OFFSET_REDUND 0
210 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
212 #define CONFIG_SYS_FLASH_CFI 1
213 #define CONFIG_FLASH_CFI_DRIVER 1
214 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
215 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
218 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
220 #define CONFIG_SYS_FLASH_PROTECTION
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
226 #if defined(CONFIG_CMD_KGDB)
227 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
230 /*-----------------------------------------------------------------------
231 * SYPCR - System Protection Control 11-9
232 * SYPCR can only be written once after reset!
233 *-----------------------------------------------------------------------
234 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
236 #if defined(CONFIG_WATCHDOG)
237 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
238 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
240 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
243 /*-----------------------------------------------------------------------
244 * SIUMCR - SIU Module Configuration 11-6
245 *-----------------------------------------------------------------------
246 * PCMCIA config., multi-function pin tri-state
248 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
250 /*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
255 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
257 /*-----------------------------------------------------------------------
258 * RTCSC - Real-Time Clock Status and Control Register 11-27
259 *-----------------------------------------------------------------------
261 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263 /*-----------------------------------------------------------------------
264 * PISCR - Periodic Interrupt Status and Control 11-31
265 *-----------------------------------------------------------------------
266 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
270 /*-----------------------------------------------------------------------
271 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
272 *-----------------------------------------------------------------------
273 * Reset PLL lock status sticky bit, timer expired status bit and timer
274 * interrupt status bit
278 #if CONFIG_XIN == 10000000
280 #if MPC8XX_HZ == 50000000
281 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
282 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
284 #elif MPC8XX_HZ == 66666666
285 #define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
286 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
289 #error unsupported CPU freq for XIN = 10MHz
292 #error unsupported freq for XIN (must be 10MHz)
297 *-----------------------------------------------------------------------
298 * SCCR - System Clock and reset Control Register 15-27
299 *-----------------------------------------------------------------------
300 * Set clock output, timebase and RTC source and divider,
301 * power management and some other internal clocks
303 * Note: When TBS == 0 the timebase is independent of current cpu clock.
306 #define SCCR_MASK SCCR_EBDF11
307 #if MPC8XX_HZ > 66666666
308 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
309 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
310 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
311 SCCR_DFALCD00 | SCCR_EBDF01)
313 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
314 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
315 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
319 /*-----------------------------------------------------------------------
321 *-----------------------------------------------------------------------
324 /*#define CONFIG_SYS_DER 0x2002000F*/
325 #define CONFIG_SYS_DER 0
328 * Init Memory Controller:
330 * BR0/1 and OR0/1 (FLASH)
333 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
334 #define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
336 /* used to re-map FLASH both when starting from SRAM or FLASH:
337 * restrict access enough to keep SRAM working (if any)
338 * but not too much to meddle with FLASH accesses
341 #define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
343 #define CONFIG_SYS_REMAP_OR_AM 0x80000000
344 #define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
346 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
347 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
349 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
350 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
351 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
353 #define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
354 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
357 * BR4 and OR4 (SDRAM)
360 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
361 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
363 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
364 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
366 #define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
367 #define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
370 * Memory Periodic Timer Prescaler
374 * Memory Periodic Timer Prescaler
376 * The Divider for PTA (refresh timer) configuration is based on an
377 * example SDRAM configuration (64 MBit, one bank). The adjustment to
378 * the number of chip selects (NCS) and the actually needed refresh
379 * rate is done by setting MPTPR.
381 * PTA is calculated from
382 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
384 * gclk CPU clock (not bus clock!)
385 * Trefresh Refresh cycle * 4 (four word bursts used)
387 * 4096 Rows from SDRAM example configuration
388 * 1000 factor s -> ms
389 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
390 * 4 Number of refresh cycles per period
391 * 64 Refresh cycle in ms per number of rows
392 * --------------------------------------------
393 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
395 * 50 MHz => 50.000.000 / Divider = 98
396 * 66 Mhz => 66.000.000 / Divider = 129
397 * 80 Mhz => 80.000.000 / Divider = 156
400 #define CONFIG_SYS_MAMR_PTA 234
403 * For 16 MBit, refresh rates could be 31.3 us
404 * (= 64 ms / 2K = 125 / quad bursts).
405 * For a simpler initialization, 15.6 us is used instead.
407 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
408 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
410 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
411 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
413 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
414 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
415 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
418 * MAMR settings for SDRAM
422 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
423 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
424 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
427 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
428 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
429 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
431 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
433 /****************************************************************/
435 #define NAND_SIZE 0x00010000 /* 64K */
436 #define NAND_BASE 0xF1000000
438 /*****************************************************************************/
440 #define CONFIG_SYS_DIRECT_FLASH_TFTP
442 /*****************************************************************************/
444 /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
445 * CxOE and CxRESET. We use the CxOE.
447 #define STATUS_LED_BIT 0x00000080 /* bit 24 */
449 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
450 #define STATUS_LED_STATE STATUS_LED_BLINKING
452 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
453 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
459 /* led_id_t is unsigned int mask */
460 typedef unsigned int led_id_t;
462 #define __led_toggle(_msk) \
464 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
467 #define __led_set(_msk, _st) \
470 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
472 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
475 #define __led_init(msk, st) __led_set(msk, st)
479 /******************************************************************************/
481 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
482 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
483 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
485 /******************************************************************************/
487 /* use board specific hardware */
488 #undef CONFIG_WATCHDOG /* watchdog disabled */
489 #define CONFIG_HW_WATCHDOG
491 /*****************************************************************************/
493 #define CONFIG_AUTO_COMPLETE 1
494 #define CONFIG_CRC32_VERIFY 1
495 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
497 /*****************************************************************************/
499 /* pass open firmware flattened device tree */
500 #define CONFIG_OF_LIBFDT 1
502 #define OF_TBCLK (MPC8XX_HZ / 16)
504 #endif /* __CONFIG_H */