2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
5 * Updates for Silicon Tx GP3 SSA board.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* mpc8560ads board configuration file */
30 /* please refer to doc/README.mpc85xx for more info */
31 /* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
38 /* High Level Configuration Options */
39 #define CONFIG_BOOKE 1 /* BOOKE */
40 #define CONFIG_E500 1 /* BOOKE e500 family */
41 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42 #define CONFIG_CPM2 1 /* has CPM2 */
43 #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
44 #define CONFIG_MPC8560 1
46 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
48 #define CONFIG_PCI /* PCI ethernet support */
49 #define CONFIG_TSEC_ENET /* tsec ethernet support*/
50 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
51 #define CONFIG_ENV_OVERWRITE
53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
58 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
60 /* Blinkin' LEDs for Robert :-)
62 #define CONFIG_SHOW_ACTIVITY 1
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_L2_CACHE /* toggle L2 cache */
68 #define CONFIG_BTB /* toggle branch predition */
70 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
72 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
74 #define CONFIG_SYS_MEMTEST_END 0x00400000
77 /* Localbus connector. There are many options that can be
78 * connected here, including sdram or lots of flash.
79 * This address, however, is used to configure a 256M local bus
80 * window that includes the Config latch below.
82 #define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
83 #define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
85 /* There are various flash options used, we configure for the largest,
86 * which is 64Mbytes. The CFI works fine and will discover the proper
89 #ifdef CONFIG_STXSSA_4M
90 #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
92 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
94 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
95 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
97 #define CONFIG_SYS_FLASH_CFI 1
98 #define CONFIG_FLASH_CFI_DRIVER 1
99 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
100 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
101 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
103 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
105 #define CONFIG_SYS_FLASH_PROTECTION
107 /* The configuration latch is Chip Select 1.
108 * It's an 8-bit latch in the lower 8 bits of the word.
110 #define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
111 #define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
112 #define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
116 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
117 #define CONFIG_SYS_RAMBOOT
119 #undef CONFIG_SYS_RAMBOOT
122 #ifdef CONFIG_SYS_RAMBOOT
123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
126 #define CONFIG_SYS_CCSRBAR 0xe0000000
127 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130 #define CONFIG_FSL_DDR1
131 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
132 #define CONFIG_DDR_SPD
133 #undef CONFIG_FSL_DDR_INTERACTIVE
135 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
136 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
138 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143 #define CONFIG_NUM_DDR_CONTROLLERS 1
144 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
145 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
147 /* I2C addresses of SPD EEPROMs */
148 #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
150 #undef CONFIG_CLOCKS_IN_MHZ
152 /* local bus definitions */
153 #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
154 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
155 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
156 #define CONFIG_SYS_LBC_LBCR 0x00000000
157 #define CONFIG_SYS_LBC_LSRT 0x20000000
158 #define CONFIG_SYS_LBC_MRTPR 0x20000000
159 #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
160 #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
161 #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
162 #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
163 #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
165 #define CONFIG_SYS_INIT_RAM_LOCK 1
166 #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
167 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
172 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
173 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
176 #define CONFIG_CONS_INDEX 2
177 #define CONFIG_SYS_NS16550
178 #define CONFIG_SYS_NS16550_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE 1
180 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
182 #define CONFIG_SYS_BAUDRATE_TABLE \
183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
188 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
189 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
190 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
191 #ifdef CONFIG_SYS_HUSH_PARSER
192 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
195 /* pass open firmware flat tree */
196 #define CONFIG_OF_LIBFDT 1
197 #define CONFIG_OF_BOARD_SETUP 1
198 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
203 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
204 #define CONFIG_HARD_I2C /* I2C with hardware support*/
205 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
206 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
207 #define CONFIG_SYS_I2C_SLAVE 0x7F
208 #undef CONFIG_SYS_I2C_NOPROBES
209 #define CONFIG_SYS_I2C_OFFSET 0x3000
212 #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
213 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
215 /* I2C EEPROM. AT24C32, we keep our environment in here.
217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
223 * Standard 8555 PCI mapping.
224 * Addresses are mapped 1-1.
226 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
227 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
228 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
229 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
230 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
231 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
233 #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
234 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
235 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
236 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
237 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
238 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
240 #if defined(CONFIG_PCI) /* PCI Ethernet card */
241 #define CONFIG_MPC85XX_PCI2 1
242 #define CONFIG_PCI_PNP /* do pci plug-and-play */
244 #define CONFIG_EEPRO100
247 #if !defined(CONFIG_PCI_PNP)
248 #define PCI_ENET0_IOADDR 0xe0000000
249 #define PCI_ENET0_MEMADDR 0xe0000000
250 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
253 #define CONFIG_PCI_SCAN_SHOW
254 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
256 #endif /* CONFIG_PCI */
258 #if defined(CONFIG_TSEC_ENET)
260 #define CONFIG_MII 1 /* MII PHY management */
262 #define CONFIG_TSEC1 1
263 #define CONFIG_TSEC1_NAME "TSEC0"
264 #define CONFIG_TSEC2 1
265 #define CONFIG_TSEC2_NAME "TSEC1"
267 #define TSEC1_PHY_ADDR 2
268 #define TSEC2_PHY_ADDR 4
269 #define TSEC1_PHYIDX 0
270 #define TSEC2_PHYIDX 0
271 #define TSEC1_FLAGS TSEC_GIGABIT
272 #define TSEC2_FLAGS TSEC_GIGABIT
273 #define CONFIG_ETHPRIME "TSEC0"
275 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
277 #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
278 #undef CONFIG_ETHER_NONE /* define if ether on something else */
279 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
281 #if (CONFIG_ETHER_INDEX == 2)
285 * - Select bus for bd/buffers
288 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
289 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
290 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
292 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
294 #define CONFIG_SYS_FCC_PSMR 0
296 #define FETH2_RST 0x01
297 #elif (CONFIG_ETHER_INDEX == 3)
298 /* need more definitions here for FE3 */
299 #define FETH3_RST 0x80
300 #endif /* CONFIG_ETHER_INDEX */
302 /* MDIO is done through the TSEC0 control.
304 #define CONFIG_MII /* MII PHY management */
305 #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
309 /* Environment - default config is in flash, see below */
310 #if 0 /* in EEPROM */
311 # define CONFIG_ENV_IS_IN_EEPROM 1
312 # define CONFIG_ENV_OFFSET 0
313 # define CONFIG_ENV_SIZE 2048
315 # define CONFIG_ENV_IS_IN_FLASH 1
316 # ifdef CONFIG_STXSSA_4M
317 # define CONFIG_ENV_SECT_SIZE 0x20000
318 # else /* default configuration - 64 MiB flash */
319 # define CONFIG_ENV_SECT_SIZE 0x40000
321 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
322 # define CONFIG_ENV_SIZE 0x4000
323 # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
324 # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
327 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
328 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
330 #define CONFIG_TIMESTAMP /* Print image info with ts */
336 #define CONFIG_BOOTP_BOOTFILESIZE
337 #define CONFIG_BOOTP_BOOTPATH
338 #define CONFIG_BOOTP_GATEWAY
339 #define CONFIG_BOOTP_HOSTNAME
343 * Command line configuration.
345 #include <config_cmd_default.h>
347 #define CONFIG_CMD_DATE
348 #define CONFIG_CMD_DHCP
349 #define CONFIG_CMD_EEPROM
350 #define CONFIG_CMD_I2C
351 #define CONFIG_CMD_NFS
352 #define CONFIG_CMD_PING
353 #define CONFIG_CMD_SNTP
354 #define CONFIG_CMD_REGINFO
356 #if defined(CONFIG_PCI)
357 #define CONFIG_CMD_PCI
360 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
361 #define CONFIG_CMD_MII
364 #if defined(CONFIG_SYS_RAMBOOT)
365 #undef CONFIG_CMD_SAVEENV
366 #undef CONFIG_CMD_LOADS
368 #define CONFIG_CMD_ELF
372 #undef CONFIG_WATCHDOG /* watchdog disabled */
375 * Miscellaneous configurable options
377 #define CONFIG_SYS_LONGHELP /* undef to save memory */
378 #define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
379 #if defined(CONFIG_CMD_KGDB)
380 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
382 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
384 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
385 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
386 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
387 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
388 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
391 * For booting Linux, the board info and command line data
392 * have to be in the first 8 MB of memory, since this is
393 * the maximum mapped by the Linux kernel during initialization.
395 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
397 #if defined(CONFIG_CMD_KGDB)
398 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
399 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
402 /*Note: change below for your network setting!!! */
403 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
404 #define CONFIG_HAS_ETH0
405 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
406 #define CONFIG_HAS_ETH1
407 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
408 #define CONFIG_HAS_ETH2
409 #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
413 * Environment in EEPROM is compatible with different flash sector sizes,
414 * but only little space is available, so we use a very simple setup.
415 * With environment in flash, we use a more powerful default configuration.
417 #ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
419 #define CONFIG_BAUDRATE 38400
421 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
422 #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
423 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
424 #define CONFIG_SERVERIP 192.168.85.1
425 #define CONFIG_IPADDR 192.168.85.60
426 #define CONFIG_GATEWAYIP 192.168.85.1
427 #define CONFIG_NETMASK 255.255.255.0
428 #define CONFIG_HOSTNAME STX_SSA
429 #define CONFIG_ROOTPATH /gppproot
430 #define CONFIG_BOOTFILE uImage
431 #define CONFIG_LOADADDR 0x1000000
433 #else /* ENV IS IN FLASH -- use a full-blown envionment */
435 #define CONFIG_BAUDRATE 115200
437 #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
439 #define CONFIG_PREBOOT "echo;" \
440 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
443 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
445 #define CONFIG_EXTRA_ENV_SETTINGS \
446 "hostname=gp3ssa\0" \
447 "bootfile=/tftpboot/gp3ssa/uImage\0" \
448 "loadaddr=400000\0" \
451 "nfsargs=setenv bootargs root=/dev/nfs rw " \
452 "nfsroot=$serverip:$rootpath\0" \
453 "ramargs=setenv bootargs root=/dev/ram rw\0" \
454 "addip=setenv bootargs $bootargs " \
455 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
456 ":$hostname:$netdev:off panic=1\0" \
457 "addcons=setenv bootargs $bootargs " \
458 "console=$consdev,$baudrate\0" \
459 "flash_nfs=run nfsargs addip addcons;" \
460 "bootm $kernel_addr\0" \
461 "flash_self=run ramargs addip addcons;" \
462 "bootm $kernel_addr $ramdisk_addr\0" \
463 "net_nfs=tftp $loadaddr $bootfile;" \
464 "run nfsargs addip addcons;bootm\0" \
465 "rootpath=/opt/eldk/ppc_85xx\0" \
466 "kernel_addr=FC000000\0" \
467 "ramdisk_addr=FC200000\0" \
469 #define CONFIG_BOOTCOMMAND "run flash_self"
471 #endif /* CONFIG_ENV_IS_IN_EEPROM */
473 #endif /* __CONFIG_H */