include/configs/stv0991.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
   4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5  */
   6
   7 #ifndef __CONFIG_STV0991_H
   8 #define __CONFIG_STV0991_H
   9 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  10
  11 /* ram memory-related information */
  12 #define PHYS_SDRAM_1                            0x00000000
  13 #define CONFIG_SYS_SDRAM_BASE                   PHYS_SDRAM_1
  14 #define PHYS_SDRAM_1_SIZE                       0x00198000
  15
  16 #define CONFIG_ENV_SIZE                         0x10000
  17 #define CONFIG_ENV_SECT_SIZE                    CONFIG_ENV_SIZE
  18 #define CONFIG_ENV_OFFSET                       0x30000
  19 #define CONFIG_ENV_ADDR                         \
  20         (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
  21 #define CONFIG_SYS_MALLOC_LEN                   (CONFIG_ENV_SIZE + 16 * 1024)
  22
  23 /* user interface */
  24 #define CONFIG_SYS_CBSIZE                       1024
  25
  26 /* MISC */
  27 #define CONFIG_SYS_LOAD_ADDR                    0x00000000
  28 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000
  29 #define CONFIG_SYS_INIT_RAM_ADDR                0x00190000
  30 #define CONFIG_SYS_INIT_SP_OFFSET               \
  31         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  32 /* U-Boot Load Address */
  33 #define CONFIG_SYS_INIT_SP_ADDR                 \
  34         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  35
  36 /* GMAC related configs */
  37
  38 #define CONFIG_DW_ALTDESCRIPTOR
  39
  40 /* Command support defines */
  41 #define CONFIG_PHY_RESET_DELAY                  10000           /* in usec */
  42
  43 #define CONFIG_SYS_MEMTEST_START               0x0000
  44 #define CONFIG_SYS_MEMTEST_END                 1024*1024
  45
  46 /* Misc configuration */
  47
  48 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
  49
  50 /*
  51 + * QSPI support
  52 + */
  53 #ifdef CONFIG_OF_CONTROL                /* QSPI is controlled via DT */
  54 #define CONFIG_CQSPI_REF_CLK            ((30/4)/2)*1000*1000
  55
  56 #endif
  57
  58 #endif /* __CONFIG_H */