1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #ifndef __CONFIG_STV0991_H
8 #define __CONFIG_STV0991_H
9 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
11 /* ram memory-related information */
12 #define PHYS_SDRAM_1 0x00000000
13 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
14 #define PHYS_SDRAM_1_SIZE 0x00198000
16 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
19 #define CONFIG_SYS_CBSIZE 1024
22 #define CONFIG_SYS_LOAD_ADDR 0x00000000
23 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000
24 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
25 #define CONFIG_SYS_INIT_SP_OFFSET \
26 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
27 /* U-Boot Load Address */
28 #define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
31 /* GMAC related configs */
33 #define CONFIG_DW_ALTDESCRIPTOR
35 /* Command support defines */
36 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
38 /* Misc configuration */
40 #define CONFIG_BOOTCOMMAND "go 0x40040000"
45 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
46 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
50 #endif /* __CONFIG_H */