1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_FSL_SERDES
22 #define CONFIG_FSL_SERDES1 0xe3000
27 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
28 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
29 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
30 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
37 * Manually set up DDR parameters
38 * consist of one chip NT5TU64M16HG from NANYA
41 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
43 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
44 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
45 | CSCONFIG_ODT_RD_NEVER \
46 | CSCONFIG_ODT_WR_ONLY_CURRENT \
47 | CSCONFIG_BANK_BIT_3 \
48 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
50 #define CONFIG_SYS_DDR_TIMING_3 0
51 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
52 | (0 << TIMING_CFG0_WRT_SHIFT) \
53 | (0 << TIMING_CFG0_RRT_SHIFT) \
54 | (0 << TIMING_CFG0_WWT_SHIFT) \
55 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
56 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
57 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
58 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
60 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
61 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
62 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
63 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
64 | (9 << TIMING_CFG1_REFREC_SHIFT) \
65 | (2 << TIMING_CFG1_WRREC_SHIFT) \
66 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
67 | (2 << TIMING_CFG1_WRTORD_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
70 | (4 << TIMING_CFG2_CPO_SHIFT) \
71 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
72 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
73 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
74 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
75 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
77 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
78 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
80 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
81 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
85 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
86 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
87 | (0x0242 << SDRAM_MODE_SD_SHIFT))
88 /* ODT 150ohm CL=4, AL=0 on SDRAM */
89 #define CONFIG_SYS_DDR_MODE2 0x00000000
94 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
95 #define CONFIG_SYS_MEMTEST_END 0x07f00000
100 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
102 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
103 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
106 * Initial RAM Base Address Setup
108 #define CONFIG_SYS_INIT_RAM_LOCK 1
109 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
110 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
111 #define CONFIG_SYS_GBL_DATA_OFFSET \
112 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
115 * Local Bus Configuration & Clock Setup
117 #define CONFIG_SYS_LBC_LBCR 0x00040000
120 * FLASH on the Local Bus
122 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
123 #define CONFIG_FLASH_CFI_LEGACY
124 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
126 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
127 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
130 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
131 #define CONFIG_SYS_MAX_FLASH_SECT 135
133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
139 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
140 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
143 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
144 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
146 #define CONFIG_SYS_FPGA_COUNT 1
148 #define CONFIG_SYS_MCLINK_MAX 3
150 #define CONFIG_SYS_FPGA_PTR \
151 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
153 #define CONFIG_SYS_FPGA_NO_RFL_HI
158 #define CONFIG_SYS_NS16550_SERIAL
159 #define CONFIG_SYS_NS16550_REG_SIZE 1
160 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
162 #define CONFIG_SYS_BAUDRATE_TABLE \
163 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
168 /* Pass open firmware flat tree */
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_FSL
173 #define CONFIG_SYS_FSL_I2C_SPEED 400000
174 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
175 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
177 #define CONFIG_PCA953X /* NXP PCA9554 */
178 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
179 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
181 #define CONFIG_PCA9698 /* NXP PCA9698 */
183 #define CONFIG_SYS_I2C_IHS
184 #define CONFIG_SYS_I2C_IHS_CH0
185 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
186 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
187 #define CONFIG_SYS_I2C_IHS_CH1
188 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
189 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
190 #define CONFIG_SYS_I2C_IHS_CH2
191 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
192 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
193 #define CONFIG_SYS_I2C_IHS_CH3
194 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
195 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
197 #ifdef CONFIG_STRIDER_CON_DP
198 #define CONFIG_SYS_I2C_IHS_DUAL
199 #define CONFIG_SYS_I2C_IHS_CH0_1
200 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
201 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
202 #define CONFIG_SYS_I2C_IHS_CH1_1
203 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
204 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
205 #define CONFIG_SYS_I2C_IHS_CH2_1
206 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
207 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
208 #define CONFIG_SYS_I2C_IHS_CH3_1
209 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
210 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
214 * Software (bit-bang) I2C driver configuration
216 #define CONFIG_SYS_I2C_SOFT
217 #define CONFIG_SOFT_I2C_READ_REPEATED_START
218 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
219 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
220 #define I2C_SOFT_DECLARATIONS2
221 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
222 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
223 #define I2C_SOFT_DECLARATIONS3
224 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
225 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
226 #define I2C_SOFT_DECLARATIONS4
227 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
228 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
229 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
230 #define I2C_SOFT_DECLARATIONS5
231 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
232 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
233 #define I2C_SOFT_DECLARATIONS6
234 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
235 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
236 #define I2C_SOFT_DECLARATIONS7
237 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
238 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
239 #define I2C_SOFT_DECLARATIONS8
240 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
241 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
243 #ifdef CONFIG_STRIDER_CON_DP
244 #define I2C_SOFT_DECLARATIONS9
245 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
246 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
247 #define I2C_SOFT_DECLARATIONS10
248 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
249 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
250 #define I2C_SOFT_DECLARATIONS11
251 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
252 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
253 #define I2C_SOFT_DECLARATIONS12
254 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
255 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
258 #ifdef CONFIG_STRIDER_CON
259 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
260 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
261 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
262 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
263 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
265 #elif defined(CONFIG_STRIDER_CON_DP)
266 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
267 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
268 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
269 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
270 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
272 #elif defined(CONFIG_STRIDER_CPU_DP)
273 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
274 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
275 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
276 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
279 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
280 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
281 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
282 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
287 void fpga_gpio_set(unsigned int bus, int pin);
288 void fpga_gpio_clear(unsigned int bus, int pin);
289 int fpga_gpio_get(unsigned int bus, int pin);
290 void fpga_control_set(unsigned int bus, int pin);
291 void fpga_control_clear(unsigned int bus, int pin);
294 #ifdef CONFIG_STRIDER_CON
295 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
296 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
297 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
298 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
299 #elif defined(CONFIG_STRIDER_CON_DP)
300 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
301 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
302 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
304 #define I2C_SDA_GPIO 0x0040
305 #define I2C_SCL_GPIO 0x0020
306 #define I2C_FPGA_IDX I2C_ADAP_HWNR
309 #ifdef CONFIG_STRIDER_CON_DP
312 if (I2C_ADAP_HWNR > 7) \
313 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
315 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
318 #define I2C_ACTIVE { }
321 #define I2C_TRISTATE { }
323 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
324 #define I2C_SDA(bit) \
327 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
329 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
331 #define I2C_SCL(bit) \
334 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
336 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
338 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
341 * Software (bit-bang) MII driver configuration
343 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
344 #define CONFIG_BITBANGMII_MULTI
349 #define CONFIG_SYS_OSD_SCREENS 1
350 #define CONFIG_SYS_DP501_DIFFERENTIAL
351 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
353 #ifdef CONFIG_STRIDER_CON_DP
354 #define CONFIG_SYS_OSD_DH
359 * Addresses are mapped 1-1.
361 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
362 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
363 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
364 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
365 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
366 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
367 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
368 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
369 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
371 /* enable PCIE clock */
372 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
374 #define CONFIG_PCI_INDIRECT_BRIDGE
377 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
378 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
383 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
384 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
387 * TSEC ethernet configuration
390 #define CONFIG_TSEC1_NAME "eTSEC0"
391 #define TSEC1_PHY_ADDR 1
392 #define TSEC1_PHYIDX 0
393 #define TSEC1_FLAGS 0
395 /* Options are: eTSEC[0-1] */
396 #define CONFIG_ETHPRIME "eTSEC0"
402 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
403 CONFIG_SYS_MONITOR_LEN)
404 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
405 #define CONFIG_ENV_SIZE 0x2000
406 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
407 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
409 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
412 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
413 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
416 * Command line configuration.
420 * Miscellaneous configurable options
422 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
423 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
425 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
427 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
430 * For booting Linux, the board info and command line data
431 * have to be in the first 256 MB of memory, since this is
432 * the maximum mapped by the Linux kernel during initialization.
434 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
437 * Environment Configuration
440 #define CONFIG_ENV_OVERWRITE
442 #if defined(CONFIG_TSEC_ENET)
443 #define CONFIG_HAS_ETH0
446 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
449 #define CONFIG_HOSTNAME "hrcon"
450 #define CONFIG_ROOTPATH "/opt/nfsroot"
451 #define CONFIG_BOOTFILE "uImage"
453 #define CONFIG_PREBOOT /* enable preboot variable */
455 #define CONFIG_EXTRA_ENV_SETTINGS \
457 "consoledev=ttyS1\0" \
458 "u-boot=u-boot.bin\0" \
459 "kernel_addr=1000000\0" \
460 "fdt_addr=C00000\0" \
461 "fdtfile=hrcon.dtb\0" \
462 "load=tftp ${loadaddr} ${u-boot}\0" \
463 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
464 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
465 " +${filesize};cp.b ${fileaddr} " \
466 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
467 "upd=run load update\0" \
469 #define CONFIG_NFSBOOTCOMMAND \
470 "setenv bootargs root=/dev/nfs rw " \
471 "nfsroot=$serverip:$rootpath " \
472 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
473 "console=$consoledev,$baudrate $othbootargs;" \
474 "tftp ${kernel_addr} $bootfile;" \
475 "tftp ${fdt_addr} $fdtfile;" \
476 "bootm ${kernel_addr} - ${fdt_addr}"
478 #define CONFIG_MMCBOOTCOMMAND \
479 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
480 "console=$consoledev,$baudrate $othbootargs;" \
481 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
482 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
483 "bootm ${kernel_addr} - ${fdt_addr}"
485 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
487 #endif /* __CONFIG_H */