1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_SYS_SICRH (\
27 SICRH_IEEE1588_A_GPIO |\
30 SICRH_IEEE1588_B_GPIO |\
35 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
36 #define CONFIG_SYS_SICRL (\
41 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
46 #define CONFIG_FSL_SERDES
47 #define CONFIG_FSL_SERDES1 0xe3000
52 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
53 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
54 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
59 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
61 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
62 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
63 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
70 * Manually set up DDR parameters
71 * consist of one chip NT5TU64M16HG from NANYA
74 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
77 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
78 | CSCONFIG_ODT_RD_NEVER \
79 | CSCONFIG_ODT_WR_ONLY_CURRENT \
80 | CSCONFIG_BANK_BIT_3 \
81 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
83 #define CONFIG_SYS_DDR_TIMING_3 0
84 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
85 | (0 << TIMING_CFG0_WRT_SHIFT) \
86 | (0 << TIMING_CFG0_RRT_SHIFT) \
87 | (0 << TIMING_CFG0_WWT_SHIFT) \
88 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
89 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
90 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
91 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
93 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
94 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
95 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
96 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
97 | (9 << TIMING_CFG1_REFREC_SHIFT) \
98 | (2 << TIMING_CFG1_WRREC_SHIFT) \
99 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
100 | (2 << TIMING_CFG1_WRTORD_SHIFT))
102 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
103 | (4 << TIMING_CFG2_CPO_SHIFT) \
104 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
105 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
106 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
107 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
108 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
110 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
111 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
113 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
114 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
118 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
119 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
120 | (0x0242 << SDRAM_MODE_SD_SHIFT))
121 /* ODT 150ohm CL=4, AL=0 on SDRAM */
122 #define CONFIG_SYS_DDR_MODE2 0x00000000
127 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
128 #define CONFIG_SYS_MEMTEST_END 0x07f00000
131 * The reserved memory
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
135 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
136 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
139 * Initial RAM Base Address Setup
141 #define CONFIG_SYS_INIT_RAM_LOCK 1
142 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
143 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
144 #define CONFIG_SYS_GBL_DATA_OFFSET \
145 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
148 * Local Bus Configuration & Clock Setup
150 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
151 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
152 #define CONFIG_SYS_LBC_LBCR 0x00040000
155 * FLASH on the Local Bus
157 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
158 #define CONFIG_FLASH_CFI_LEGACY
159 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
161 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
162 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
165 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
166 #define CONFIG_SYS_MAX_FLASH_SECT 135
168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
174 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
175 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
178 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
179 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
181 #define CONFIG_SYS_FPGA_COUNT 1
183 #define CONFIG_SYS_MCLINK_MAX 3
185 #define CONFIG_SYS_FPGA_PTR \
186 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
188 #define CONFIG_SYS_FPGA_NO_RFL_HI
193 #define CONFIG_SYS_NS16550_SERIAL
194 #define CONFIG_SYS_NS16550_REG_SIZE 1
195 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
197 #define CONFIG_SYS_BAUDRATE_TABLE \
198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
203 /* Pass open firmware flat tree */
206 #define CONFIG_SYS_I2C
207 #define CONFIG_SYS_I2C_FSL
208 #define CONFIG_SYS_FSL_I2C_SPEED 400000
209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
212 #define CONFIG_PCA953X /* NXP PCA9554 */
213 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
214 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
216 #define CONFIG_PCA9698 /* NXP PCA9698 */
218 #define CONFIG_SYS_I2C_IHS
219 #define CONFIG_SYS_I2C_IHS_CH0
220 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
221 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
222 #define CONFIG_SYS_I2C_IHS_CH1
223 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
224 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
225 #define CONFIG_SYS_I2C_IHS_CH2
226 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
227 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
228 #define CONFIG_SYS_I2C_IHS_CH3
229 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
230 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
232 #ifdef CONFIG_STRIDER_CON_DP
233 #define CONFIG_SYS_I2C_IHS_DUAL
234 #define CONFIG_SYS_I2C_IHS_CH0_1
235 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
236 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
237 #define CONFIG_SYS_I2C_IHS_CH1_1
238 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
239 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
240 #define CONFIG_SYS_I2C_IHS_CH2_1
241 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
242 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
243 #define CONFIG_SYS_I2C_IHS_CH3_1
244 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
245 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
249 * Software (bit-bang) I2C driver configuration
251 #define CONFIG_SYS_I2C_SOFT
252 #define CONFIG_SOFT_I2C_READ_REPEATED_START
253 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
254 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
255 #define I2C_SOFT_DECLARATIONS2
256 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
257 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
258 #define I2C_SOFT_DECLARATIONS3
259 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
260 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
261 #define I2C_SOFT_DECLARATIONS4
262 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
263 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
264 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
265 #define I2C_SOFT_DECLARATIONS5
266 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
267 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
268 #define I2C_SOFT_DECLARATIONS6
269 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
270 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
271 #define I2C_SOFT_DECLARATIONS7
272 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
273 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
274 #define I2C_SOFT_DECLARATIONS8
275 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
276 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
278 #ifdef CONFIG_STRIDER_CON_DP
279 #define I2C_SOFT_DECLARATIONS9
280 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
281 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
282 #define I2C_SOFT_DECLARATIONS10
283 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
284 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
285 #define I2C_SOFT_DECLARATIONS11
286 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
287 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
288 #define I2C_SOFT_DECLARATIONS12
289 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
290 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
293 #ifdef CONFIG_STRIDER_CON
294 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
295 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
296 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
297 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
298 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
300 #elif defined(CONFIG_STRIDER_CON_DP)
301 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
302 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
303 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
304 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
305 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
307 #elif defined(CONFIG_STRIDER_CPU_DP)
308 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
309 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
310 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
311 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
314 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
315 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
316 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
317 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
322 void fpga_gpio_set(unsigned int bus, int pin);
323 void fpga_gpio_clear(unsigned int bus, int pin);
324 int fpga_gpio_get(unsigned int bus, int pin);
325 void fpga_control_set(unsigned int bus, int pin);
326 void fpga_control_clear(unsigned int bus, int pin);
329 #ifdef CONFIG_STRIDER_CON
330 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
331 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
332 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
333 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
334 #elif defined(CONFIG_STRIDER_CON_DP)
335 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
336 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
337 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
339 #define I2C_SDA_GPIO 0x0040
340 #define I2C_SCL_GPIO 0x0020
341 #define I2C_FPGA_IDX I2C_ADAP_HWNR
344 #ifdef CONFIG_STRIDER_CON_DP
347 if (I2C_ADAP_HWNR > 7) \
348 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
350 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
353 #define I2C_ACTIVE { }
356 #define I2C_TRISTATE { }
358 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
359 #define I2C_SDA(bit) \
362 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
364 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
366 #define I2C_SCL(bit) \
369 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
371 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
373 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
376 * Software (bit-bang) MII driver configuration
378 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
379 #define CONFIG_BITBANGMII_MULTI
384 #define CONFIG_SYS_OSD_SCREENS 1
385 #define CONFIG_SYS_DP501_DIFFERENTIAL
386 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
388 #ifdef CONFIG_STRIDER_CON_DP
389 #define CONFIG_SYS_OSD_DH
394 * Addresses are mapped 1-1.
396 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
397 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
399 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
400 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
401 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
402 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
403 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
404 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
406 /* enable PCIE clock */
407 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
409 #define CONFIG_PCI_INDIRECT_BRIDGE
412 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
413 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
418 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
419 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
422 * TSEC ethernet configuration
425 #define CONFIG_TSEC1_NAME "eTSEC0"
426 #define TSEC1_PHY_ADDR 1
427 #define TSEC1_PHYIDX 0
428 #define TSEC1_FLAGS 0
430 /* Options are: eTSEC[0-1] */
431 #define CONFIG_ETHPRIME "eTSEC0"
437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
438 CONFIG_SYS_MONITOR_LEN)
439 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
440 #define CONFIG_ENV_SIZE 0x2000
441 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
442 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
444 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
447 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
448 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
451 * Command line configuration.
455 * Miscellaneous configurable options
457 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
458 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
460 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
465 * For booting Linux, the board info and command line data
466 * have to be in the first 256 MB of memory, since this is
467 * the maximum mapped by the Linux kernel during initialization.
469 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
472 * Environment Configuration
475 #define CONFIG_ENV_OVERWRITE
477 #if defined(CONFIG_TSEC_ENET)
478 #define CONFIG_HAS_ETH0
481 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
484 #define CONFIG_HOSTNAME "hrcon"
485 #define CONFIG_ROOTPATH "/opt/nfsroot"
486 #define CONFIG_BOOTFILE "uImage"
488 #define CONFIG_PREBOOT /* enable preboot variable */
490 #define CONFIG_EXTRA_ENV_SETTINGS \
492 "consoledev=ttyS1\0" \
493 "u-boot=u-boot.bin\0" \
494 "kernel_addr=1000000\0" \
495 "fdt_addr=C00000\0" \
496 "fdtfile=hrcon.dtb\0" \
497 "load=tftp ${loadaddr} ${u-boot}\0" \
498 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
499 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
500 " +${filesize};cp.b ${fileaddr} " \
501 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
502 "upd=run load update\0" \
504 #define CONFIG_NFSBOOTCOMMAND \
505 "setenv bootargs root=/dev/nfs rw " \
506 "nfsroot=$serverip:$rootpath " \
507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
508 "console=$consoledev,$baudrate $othbootargs;" \
509 "tftp ${kernel_addr} $bootfile;" \
510 "tftp ${fdt_addr} $fdtfile;" \
511 "bootm ${kernel_addr} - ${fdt_addr}"
513 #define CONFIG_MMCBOOTCOMMAND \
514 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
517 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
518 "bootm ${kernel_addr} - ${fdt_addr}"
520 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
522 #endif /* __CONFIG_H */