1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_FSL_SERDES
22 #define CONFIG_FSL_SERDES1 0xe3000
27 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
29 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
36 * Manually set up DDR parameters
37 * consist of one chip NT5TU64M16HG from NANYA
40 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
42 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
43 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
44 | CSCONFIG_ODT_RD_NEVER \
45 | CSCONFIG_ODT_WR_ONLY_CURRENT \
46 | CSCONFIG_BANK_BIT_3 \
47 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
49 #define CONFIG_SYS_DDR_TIMING_3 0
50 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
51 | (0 << TIMING_CFG0_WRT_SHIFT) \
52 | (0 << TIMING_CFG0_RRT_SHIFT) \
53 | (0 << TIMING_CFG0_WWT_SHIFT) \
54 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
55 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
56 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
57 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
60 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
61 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
62 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
63 | (9 << TIMING_CFG1_REFREC_SHIFT) \
64 | (2 << TIMING_CFG1_WRREC_SHIFT) \
65 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
66 | (2 << TIMING_CFG1_WRTORD_SHIFT))
68 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
69 | (4 << TIMING_CFG2_CPO_SHIFT) \
70 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
71 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
72 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
73 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
74 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
76 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
77 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
79 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
80 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
84 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
85 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
86 | (0x0242 << SDRAM_MODE_SD_SHIFT))
87 /* ODT 150ohm CL=4, AL=0 on SDRAM */
88 #define CONFIG_SYS_DDR_MODE2 0x00000000
93 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
94 #define CONFIG_SYS_MEMTEST_END 0x07f00000
99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
101 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
102 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
105 * Initial RAM Base Address Setup
107 #define CONFIG_SYS_INIT_RAM_LOCK 1
108 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
109 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
110 #define CONFIG_SYS_GBL_DATA_OFFSET \
111 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114 * FLASH on the Local Bus
116 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
117 #define CONFIG_FLASH_CFI_LEGACY
118 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
120 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
121 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
125 #define CONFIG_SYS_MAX_FLASH_SECT 135
127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
133 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
134 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
137 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
138 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
140 #define CONFIG_SYS_FPGA_COUNT 1
142 #define CONFIG_SYS_MCLINK_MAX 3
144 #define CONFIG_SYS_FPGA_PTR \
145 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
147 #define CONFIG_SYS_FPGA_NO_RFL_HI
152 #define CONFIG_SYS_NS16550_SERIAL
153 #define CONFIG_SYS_NS16550_REG_SIZE 1
154 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
156 #define CONFIG_SYS_BAUDRATE_TABLE \
157 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
162 /* Pass open firmware flat tree */
165 #define CONFIG_SYS_I2C
166 #define CONFIG_SYS_I2C_FSL
167 #define CONFIG_SYS_FSL_I2C_SPEED 400000
168 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
169 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
171 #define CONFIG_PCA953X /* NXP PCA9554 */
172 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
173 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
175 #define CONFIG_PCA9698 /* NXP PCA9698 */
177 #define CONFIG_SYS_I2C_IHS
178 #define CONFIG_SYS_I2C_IHS_CH0
179 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
180 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
181 #define CONFIG_SYS_I2C_IHS_CH1
182 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
183 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
184 #define CONFIG_SYS_I2C_IHS_CH2
185 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
186 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
187 #define CONFIG_SYS_I2C_IHS_CH3
188 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
189 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
191 #ifdef CONFIG_STRIDER_CON_DP
192 #define CONFIG_SYS_I2C_IHS_DUAL
193 #define CONFIG_SYS_I2C_IHS_CH0_1
194 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
195 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
196 #define CONFIG_SYS_I2C_IHS_CH1_1
197 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
198 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
199 #define CONFIG_SYS_I2C_IHS_CH2_1
200 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
201 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
202 #define CONFIG_SYS_I2C_IHS_CH3_1
203 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
204 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
208 * Software (bit-bang) I2C driver configuration
210 #define CONFIG_SYS_I2C_SOFT
211 #define CONFIG_SOFT_I2C_READ_REPEATED_START
212 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
213 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
214 #define I2C_SOFT_DECLARATIONS2
215 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
216 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
217 #define I2C_SOFT_DECLARATIONS3
218 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
219 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
220 #define I2C_SOFT_DECLARATIONS4
221 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
222 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
223 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
224 #define I2C_SOFT_DECLARATIONS5
225 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
226 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
227 #define I2C_SOFT_DECLARATIONS6
228 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
229 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
230 #define I2C_SOFT_DECLARATIONS7
231 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
232 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
233 #define I2C_SOFT_DECLARATIONS8
234 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
235 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
237 #ifdef CONFIG_STRIDER_CON_DP
238 #define I2C_SOFT_DECLARATIONS9
239 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
240 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
241 #define I2C_SOFT_DECLARATIONS10
242 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
243 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
244 #define I2C_SOFT_DECLARATIONS11
245 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
246 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
247 #define I2C_SOFT_DECLARATIONS12
248 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
249 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
252 #ifdef CONFIG_STRIDER_CON
253 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
254 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
255 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
256 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
257 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
259 #elif defined(CONFIG_STRIDER_CON_DP)
260 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
261 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
262 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
263 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
264 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
266 #elif defined(CONFIG_STRIDER_CPU_DP)
267 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
268 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
269 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
270 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
273 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
274 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
275 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
276 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
281 void fpga_gpio_set(unsigned int bus, int pin);
282 void fpga_gpio_clear(unsigned int bus, int pin);
283 int fpga_gpio_get(unsigned int bus, int pin);
284 void fpga_control_set(unsigned int bus, int pin);
285 void fpga_control_clear(unsigned int bus, int pin);
288 #ifdef CONFIG_STRIDER_CON
289 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
290 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
291 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
292 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
293 #elif defined(CONFIG_STRIDER_CON_DP)
294 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
295 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
296 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
298 #define I2C_SDA_GPIO 0x0040
299 #define I2C_SCL_GPIO 0x0020
300 #define I2C_FPGA_IDX I2C_ADAP_HWNR
303 #ifdef CONFIG_STRIDER_CON_DP
306 if (I2C_ADAP_HWNR > 7) \
307 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
309 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
312 #define I2C_ACTIVE { }
315 #define I2C_TRISTATE { }
317 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
318 #define I2C_SDA(bit) \
321 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
323 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
325 #define I2C_SCL(bit) \
328 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
330 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
332 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
335 * Software (bit-bang) MII driver configuration
337 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
338 #define CONFIG_BITBANGMII_MULTI
343 #define CONFIG_SYS_OSD_SCREENS 1
344 #define CONFIG_SYS_DP501_DIFFERENTIAL
345 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
347 #ifdef CONFIG_STRIDER_CON_DP
348 #define CONFIG_SYS_OSD_DH
353 * Addresses are mapped 1-1.
355 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
356 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
357 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
358 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
359 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
360 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
361 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
362 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
363 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
365 /* enable PCIE clock */
366 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
368 #define CONFIG_PCI_INDIRECT_BRIDGE
371 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
372 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
377 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
378 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
381 * TSEC ethernet configuration
384 #define CONFIG_TSEC1_NAME "eTSEC0"
385 #define TSEC1_PHY_ADDR 1
386 #define TSEC1_PHYIDX 0
387 #define TSEC1_FLAGS 0
389 /* Options are: eTSEC[0-1] */
390 #define CONFIG_ETHPRIME "eTSEC0"
396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
397 CONFIG_SYS_MONITOR_LEN)
398 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
399 #define CONFIG_ENV_SIZE 0x2000
400 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
401 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
403 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
407 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
410 * Command line configuration.
414 * Miscellaneous configurable options
416 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
417 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
419 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
421 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
424 * For booting Linux, the board info and command line data
425 * have to be in the first 256 MB of memory, since this is
426 * the maximum mapped by the Linux kernel during initialization.
428 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
431 * Environment Configuration
434 #define CONFIG_ENV_OVERWRITE
436 #if defined(CONFIG_TSEC_ENET)
437 #define CONFIG_HAS_ETH0
440 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
443 #define CONFIG_HOSTNAME "hrcon"
444 #define CONFIG_ROOTPATH "/opt/nfsroot"
445 #define CONFIG_BOOTFILE "uImage"
447 #define CONFIG_PREBOOT /* enable preboot variable */
449 #define CONFIG_EXTRA_ENV_SETTINGS \
451 "consoledev=ttyS1\0" \
452 "u-boot=u-boot.bin\0" \
453 "kernel_addr=1000000\0" \
454 "fdt_addr=C00000\0" \
455 "fdtfile=hrcon.dtb\0" \
456 "load=tftp ${loadaddr} ${u-boot}\0" \
457 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
458 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
459 " +${filesize};cp.b ${fileaddr} " \
460 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
461 "upd=run load update\0" \
463 #define CONFIG_NFSBOOTCOMMAND \
464 "setenv bootargs root=/dev/nfs rw " \
465 "nfsroot=$serverip:$rootpath " \
466 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
467 "console=$consoledev,$baudrate $othbootargs;" \
468 "tftp ${kernel_addr} $bootfile;" \
469 "tftp ${fdt_addr} $fdtfile;" \
470 "bootm ${kernel_addr} - ${fdt_addr}"
472 #define CONFIG_MMCBOOTCOMMAND \
473 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
474 "console=$consoledev,$baudrate $othbootargs;" \
475 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
476 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
477 "bootm ${kernel_addr} - ${fdt_addr}"
479 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
481 #endif /* __CONFIG_H */