include/configs/strider.h

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  17 #define CONFIG_MPC830x          1 /* MPC830x family */
  18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  19 #define CONFIG_STRIDER          1 /* STRIDER board specific */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  22
  23 #ifdef CONFIG_STRIDER_CPU
  24 #define CONFIG_IDENT_STRING     " strider cpu 0.01"
  25 #elif defined(CONFIG_STRIDER_CON_DP)
  26 #define CONFIG_IDENT_STRING     " strider con dp 0.01"
  27 #else
  28 #define CONFIG_IDENT_STRING     " strider con 0.01"
  29 #endif
  30
  31 #define CONFIG_BOARD_EARLY_INIT_F
  32 #define CONFIG_BOARD_EARLY_INIT_R
  33 #define CONFIG_LAST_STAGE_INIT
  34
  35 #define CONFIG_MMC
  36 #define CONFIG_FSL_ESDHC
  37 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  38 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  39
  40 #define CONFIG_GENERIC_MMC
  41 #define CONFIG_DOS_PARTITION
  42
  43 #define CONFIG_SYS_ALT_MEMTEST
  44
  45 #define CONFIG_CMD_FPGAD
  46 #define CONFIG_CMD_IOLOOP
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  52 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  53
  54 /*
  55  * Hardware Reset Configuration Word
  56  * if CLKIN is 66.66MHz, then
  57  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  58  * We choose the A type silicon as default, so the core is 400Mhz.
  59  */
  60 #define CONFIG_SYS_HRCW_LOW (\
  61         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  62         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  63         HRCWL_SVCOD_DIV_2 |\
  64         HRCWL_CSB_TO_CLKIN_4X1 |\
  65         HRCWL_CORE_TO_CSB_3X1)
  66 /*
  67  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  68  * in 8308's HRCWH according to the manual, but original Freescale's
  69  * code has them and I've expirienced some problems using the board
  70  * with BDI3000 attached when I've tried to set these bits to zero
  71  * (UART doesn't work after the 'reset run' command).
  72  */
  73 #define CONFIG_SYS_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_CORE_ENABLE |\
  77         HRCWH_FROM_0XFFF00100 |\
  78         HRCWH_BOOTSEQ_DISABLE |\
  79         HRCWH_SW_WATCHDOG_DISABLE |\
  80         HRCWH_ROM_LOC_LOCAL_16BIT |\
  81         HRCWH_RL_EXT_LEGACY |\
  82         HRCWH_TSEC1M_IN_MII |\
  83         HRCWH_TSEC2M_IN_RGMII |\
  84         HRCWH_BIG_ENDIAN)
  85
  86 /*
  87  * System IO Config
  88  */
  89 #define CONFIG_SYS_SICRH (\
  90         SICRH_ESDHC_A_SD |\
  91         SICRH_ESDHC_B_SD |\
  92         SICRH_ESDHC_C_SD |\
  93         SICRH_GPIO_A_GPIO |\
  94         SICRH_GPIO_B_GPIO |\
  95         SICRH_IEEE1588_A_GPIO |\
  96         SICRH_USB |\
  97         SICRH_GTM_GPIO |\
  98         SICRH_IEEE1588_B_GPIO |\
  99         SICRH_ETSEC2_GPIO |\
 100         SICRH_GPIOSEL_1 |\
 101         SICRH_TMROBI_V3P3 |\
 102         SICRH_TSOBI1_V2P5 |\
 103         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
 104 #define CONFIG_SYS_SICRL (\
 105         SICRL_SPI_PF0 |\
 106         SICRL_UART_PF0 |\
 107         SICRL_IRQ_PF0 |\
 108         SICRL_I2C2_PF0 |\
 109         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
 110
 111 /*
 112  * IMMR new address
 113  */
 114 #define CONFIG_SYS_IMMR         0xE0000000
 115
 116 /*
 117  * SERDES
 118  */
 119 #define CONFIG_FSL_SERDES
 120 #define CONFIG_FSL_SERDES1      0xe3000
 121
 122 /*
 123  * Arbiter Setup
 124  */
 125 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 126 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 127 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 128
 129 /*
 130  * DDR Setup
 131  */
 132 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 133 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 134 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 135 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 136 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 137                                 | DDRCDR_PZ_LOZ \
 138                                 | DDRCDR_NZ_LOZ \
 139                                 | DDRCDR_ODT \
 140                                 | DDRCDR_Q_DRN)
 141                                 /* 0x7b880001 */
 142 /*
 143  * Manually set up DDR parameters
 144  * consist of one chip NT5TU64M16HG from NANYA
 145  */
 146
 147 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 148
 149 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 150 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 151                                 | CSCONFIG_ODT_RD_NEVER \
 152                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 153                                 | CSCONFIG_BANK_BIT_3 \
 154                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 155                                 /* 0x80010102 */
 156 #define CONFIG_SYS_DDR_TIMING_3 0
 157 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 158                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 159                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 160                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 161                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 162                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 163                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 164                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 165                                 /* 0x00260802 */
 166 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 167                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 168                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 169                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 170                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 171                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 172                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 173                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 174                                 /* 0x26279222 */
 175 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 176                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 177                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 178                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 179                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 180                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 181                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 182                                 /* 0x021848c5 */
 183 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 184                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 185                                 /* 0x08240100 */
 186 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 187                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 188                                 | SDRAM_CFG_DBW_16)
 189                                 /* 0x43100000 */
 190
 191 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 192 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 193                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 194                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 195 #define CONFIG_SYS_DDR_MODE2            0x00000000
 196
 197 /*
 198  * Memory test
 199  */
 200 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 201 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 202
 203 /*
 204  * The reserved memory
 205  */
 206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 207
 208 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 209 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 210
 211 /*
 212  * Initial RAM Base Address Setup
 213  */
 214 #define CONFIG_SYS_INIT_RAM_LOCK        1
 215 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 216 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 218         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 219
 220 /*
 221  * Local Bus Configuration & Clock Setup
 222  */
 223 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 224 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 225 #define CONFIG_SYS_LBC_LBCR             0x00040000
 226
 227 /*
 228  * FLASH on the Local Bus
 229  */
 230 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 231 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 232 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 233 #define CONFIG_FLASH_CFI_LEGACY
 234 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 235
 236 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 237 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 238 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 239
 240 /* Window base at flash base */
 241 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 242 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 243
 244 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 245                                 | BR_PS_16      /* 16 bit port */ \
 246                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 247                                 | BR_V)         /* valid */
 248 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 249                                 | OR_UPM_XAM \
 250                                 | OR_GPCM_CSNT \
 251                                 | OR_GPCM_ACS_DIV2 \
 252                                 | OR_GPCM_XACS \
 253                                 | OR_GPCM_SCY_15 \
 254                                 | OR_GPCM_TRLX_SET \
 255                                 | OR_GPCM_EHTR_SET)
 256
 257 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 258 #define CONFIG_SYS_MAX_FLASH_SECT       135
 259
 260 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 261 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 262
 263 /*
 264  * FPGA
 265  */
 266 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 267 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 268
 269 /* Window base at FPGA base */
 270 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 271 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 272
 273 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 274                                 | BR_PS_16      /* 16 bit port */ \
 275                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 276                                 | BR_V)         /* valid */
 277
 278 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 279                                 | OR_UPM_XAM \
 280                                 | OR_GPCM_CSNT \
 281                                 | OR_GPCM_SCY_5 \
 282                                 | OR_GPCM_TRLX_CLEAR \
 283                                 | OR_GPCM_EHTR_CLEAR)
 284
 285 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 286 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 287
 288 #define CONFIG_SYS_FPGA_COUNT           1
 289
 290 #define CONFIG_SYS_MCLINK_MAX           3
 291
 292 #define CONFIG_SYS_FPGA_PTR \
 293         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 294
 295 #define CONFIG_SYS_FPGA_NO_RFL_HI
 296
 297 /*
 298  * Serial Port
 299  */
 300 #define CONFIG_CONS_INDEX       2
 301 #define CONFIG_SYS_NS16550_SERIAL
 302 #define CONFIG_SYS_NS16550_REG_SIZE     1
 303 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 304
 305 #define CONFIG_SYS_BAUDRATE_TABLE  \
 306         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 307
 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 310
 311 /* Pass open firmware flat tree */
 312
 313 /* I2C */
 314 #define CONFIG_SYS_I2C
 315 #define CONFIG_SYS_I2C_FSL
 316 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 317 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 318 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 319
 320 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 321 #define CONFIG_CMD_PCA953X
 322 #define CONFIG_CMD_PCA953X_INFO
 323 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
 324                                           {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
 325
 326 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 327
 328 #define CONFIG_SYS_I2C_IHS
 329 #define CONFIG_SYS_I2C_IHS_CH0
 330 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 331 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 332 #define CONFIG_SYS_I2C_IHS_CH1
 333 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 334 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 335 #define CONFIG_SYS_I2C_IHS_CH2
 336 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 337 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 338 #define CONFIG_SYS_I2C_IHS_CH3
 339 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 340 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 341
 342 #ifdef CONFIG_STRIDER_CON_DP
 343 #define CONFIG_SYS_I2C_IHS_DUAL
 344 #define CONFIG_SYS_I2C_IHS_CH0_1
 345 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 346 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 347 #define CONFIG_SYS_I2C_IHS_CH1_1
 348 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 349 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 350 #define CONFIG_SYS_I2C_IHS_CH2_1
 351 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 352 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 353 #define CONFIG_SYS_I2C_IHS_CH3_1
 354 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 355 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 356 #endif
 357
 358 /*
 359  * Software (bit-bang) I2C driver configuration
 360  */
 361 #define CONFIG_SYS_I2C_SOFT
 362 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 363 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 364 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 365 #define I2C_SOFT_DECLARATIONS2
 366 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 367 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 368 #define I2C_SOFT_DECLARATIONS3
 369 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 370 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 371 #define I2C_SOFT_DECLARATIONS4
 372 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 373 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 374 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
 375 #define I2C_SOFT_DECLARATIONS5
 376 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 378 #define I2C_SOFT_DECLARATIONS6
 379 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 380 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 381 #define I2C_SOFT_DECLARATIONS7
 382 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 383 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 384 #define I2C_SOFT_DECLARATIONS8
 385 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 386 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 387 #endif
 388 #ifdef CONFIG_STRIDER_CON_DP
 389 #define I2C_SOFT_DECLARATIONS9
 390 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 391 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 392 #define I2C_SOFT_DECLARATIONS10
 393 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 394 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 395 #define I2C_SOFT_DECLARATIONS11
 396 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 397 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 398 #define I2C_SOFT_DECLARATIONS12
 399 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 400 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 401 #endif
 402
 403 #ifdef CONFIG_STRIDER_CON
 404 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
 405 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
 406 #define CONFIG_SYS_ADV7611_I2C                  {5, 6, 7, 8}
 407 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 408 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 409                                                   {12, 0x4c} }
 410 #elif defined(CONFIG_STRIDER_CON_DP)
 411 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 412 #define CONFIG_SYS_CH7301_I2C                   {1, 3, 5, 7}
 413 #define CONFIG_SYS_ADV7611_I2C                  {1, 3, 5, 7}
 414 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 415 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
 416                                                   {12, 0x4c} }
 417 #else
 418 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
 419 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
 420 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 421 #define CONFIG_STRIDER_FANS                     { {2, 0x18}, {3, 0x18}, \
 422                                                   {4, 0x18} }
 423 #endif
 424
 425 #ifndef __ASSEMBLY__
 426 void fpga_gpio_set(unsigned int bus, int pin);
 427 void fpga_gpio_clear(unsigned int bus, int pin);
 428 int fpga_gpio_get(unsigned int bus, int pin);
 429 void fpga_control_set(unsigned int bus, int pin);
 430 void fpga_control_clear(unsigned int bus, int pin);
 431 #endif
 432
 433 #ifdef CONFIG_STRIDER_CON
 434 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
 435 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
 436 #define I2C_FPGA_IDX    ((I2C_ADAP_HWNR > 3) ? \
 437                          (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
 438 #elif defined(CONFIG_STRIDER_CON_DP)
 439 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 440 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 441 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 442 #else
 443 #define I2C_SDA_GPIO    0x0040
 444 #define I2C_SCL_GPIO    0x0020
 445 #define I2C_FPGA_IDX    I2C_ADAP_HWNR
 446 #endif
 447
 448 #ifdef CONFIG_STRIDER_CON_DP
 449 #define I2C_ACTIVE \
 450         do { \
 451                 if (I2C_ADAP_HWNR > 7) \
 452                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 453                 else \
 454                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 455         } while (0)
 456 #else
 457 #define I2C_ACTIVE      { }
 458 #endif
 459
 460 #define I2C_TRISTATE    { }
 461 #define I2C_READ \
 462         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 463 #define I2C_SDA(bit) \
 464         do { \
 465                 if (bit) \
 466                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 467                 else \
 468                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 469         } while (0)
 470 #define I2C_SCL(bit) \
 471         do { \
 472                 if (bit) \
 473                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 474                 else \
 475                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 476         } while (0)
 477 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 478
 479 /*
 480  * Software (bit-bang) MII driver configuration
 481  */
 482 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 483 #define CONFIG_BITBANGMII_MULTI
 484
 485 /*
 486  * OSD Setup
 487  */
 488 #define CONFIG_SYS_OSD_SCREENS          1
 489 #define CONFIG_SYS_DP501_DIFFERENTIAL
 490 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 491
 492 #ifdef CONFIG_STRIDER_CON_DP
 493 #define CONFIG_SYS_OSD_DH
 494 #endif
 495
 496 /*
 497  * General PCI
 498  * Addresses are mapped 1-1.
 499  */
 500 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 501 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 502 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 503 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 504 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 505 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 506 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 507 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 508 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 509
 510 /* enable PCIE clock */
 511 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 512
 513 #define CONFIG_PCI
 514 #define CONFIG_PCI_INDIRECT_BRIDGE
 515 #define CONFIG_PCIE
 516
 517 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 518
 519 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 520 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 521
 522 /*
 523  * TSEC
 524  */
 525 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 526 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 527 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 528
 529 /*
 530  * TSEC ethernet configuration
 531  */
 532 #define CONFIG_MII              1 /* MII PHY management */
 533 #define CONFIG_TSEC1
 534 #define CONFIG_TSEC1_NAME       "eTSEC0"
 535 #define TSEC1_PHY_ADDR          1
 536 #define TSEC1_PHYIDX            0
 537 #define TSEC1_FLAGS             0
 538
 539 /* Options are: eTSEC[0-1] */
 540 #define CONFIG_ETHPRIME         "eTSEC0"
 541
 542 /*
 543  * Environment
 544  */
 545 #if 1
 546 #define CONFIG_ENV_IS_IN_FLASH  1
 547 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 548                                  CONFIG_SYS_MONITOR_LEN)
 549 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 550 #define CONFIG_ENV_SIZE         0x2000
 551 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 552 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 553 #else
 554 #define CONFIG_ENV_IS_NOWHERE
 555 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 556 #endif
 557
 558 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 559 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 560
 561 /*
 562  * Command line configuration.
 563  */
 564 #define CONFIG_CMD_PCI
 565
 566 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 567 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 568
 569 /*
 570  * Miscellaneous configurable options
 571  */
 572 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 573 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 574 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 575
 576 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
 577
 578 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 579
 580 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 581
 582 /* Print Buffer Size */
 583 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 584 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 585 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 586
 587 /*
 588  * For booting Linux, the board info and command line data
 589  * have to be in the first 256 MB of memory, since this is
 590  * the maximum mapped by the Linux kernel during initialization.
 591  */
 592 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 593
 594 /*
 595  * Core HID Setup
 596  */
 597 #define CONFIG_SYS_HID0_INIT    0x000000000
 598 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 599                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 600                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 601 #define CONFIG_SYS_HID2         HID2_HBE
 602
 603 /*
 604  * MMU Setup
 605  */
 606
 607 /* DDR: cache cacheable */
 608 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 609                                         BATL_MEMCOHERENCE)
 610 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 611                                         BATU_VS | BATU_VP)
 612 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 613 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 614
 615 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 616 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 617                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 618 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 619                                         BATU_VP)
 620 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 621 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 622
 623 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 624 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 625                                         BATL_MEMCOHERENCE)
 626 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 627                                         BATU_VS | BATU_VP)
 628 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 629                                         BATL_CACHEINHIBIT | \
 630                                         BATL_GUARDEDSTORAGE)
 631 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 632
 633 /* Stack in dcache: cacheable, no memory coherence */
 634 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 635 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 636                                         BATU_VS | BATU_VP)
 637 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 638 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 639
 640 /*
 641  * Environment Configuration
 642  */
 643
 644 #define CONFIG_ENV_OVERWRITE
 645
 646 #if defined(CONFIG_TSEC_ENET)
 647 #define CONFIG_HAS_ETH0
 648 #endif
 649
 650 #define CONFIG_BAUDRATE 115200
 651
 652 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 653
 654 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 655
 656 #define CONFIG_HOSTNAME         hrcon
 657 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 658 #define CONFIG_BOOTFILE         "uImage"
 659
 660 #define CONFIG_PREBOOT          /* enable preboot variable */
 661
 662 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 663         "netdev=eth0\0"                                                 \
 664         "consoledev=ttyS1\0"                                            \
 665         "u-boot=u-boot.bin\0"                                           \
 666         "kernel_addr=1000000\0"                                 \
 667         "fdt_addr=C00000\0"                                             \
 668         "fdtfile=hrcon.dtb\0"                           \
 669         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 670         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 671                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 672                 " +${filesize};cp.b ${fileaddr} "                       \
 673                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 674         "upd=run load update\0"                                         \
 675
 676 #define CONFIG_NFSBOOTCOMMAND                                           \
 677         "setenv bootargs root=/dev/nfs rw "                             \
 678         "nfsroot=$serverip:$rootpath "                                  \
 679         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 680         "console=$consoledev,$baudrate $othbootargs;"                   \
 681         "tftp ${kernel_addr} $bootfile;"                                \
 682         "tftp ${fdt_addr} $fdtfile;"                                    \
 683         "bootm ${kernel_addr} - ${fdt_addr}"
 684
 685 #define CONFIG_MMCBOOTCOMMAND                                           \
 686         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 687         "console=$consoledev,$baudrate $othbootargs;"                   \
 688         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 689         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 690         "bootm ${kernel_addr} - ${fdt_addr}"
 691
 692 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 693
 694 #endif  /* __CONFIG_H */