Convert CONFIG_BOARD_EARLY_INIT_F to Kconfig
[platform/kernel/u-boot.git] / include / configs / strider.h
1 /*
2  * (C) Copyright 2014
3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
4  *
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1 /* E300 family */
16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
17 #define CONFIG_MPC830x          1 /* MPC830x family */
18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
19 #define CONFIG_STRIDER          1 /* STRIDER board specific */
20
21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
22
23 #define CONFIG_BOARD_EARLY_INIT_R
24 #define CONFIG_LAST_STAGE_INIT
25
26 #define CONFIG_FSL_ESDHC
27 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
28
29 #define CONFIG_GENERIC_MMC
30 #define CONFIG_DOS_PARTITION
31
32 #define CONFIG_SYS_ALT_MEMTEST
33
34 #define CONFIG_CMD_FPGAD
35 #define CONFIG_CMD_IOLOOP
36
37 /*
38  * System Clock Setup
39  */
40 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
41 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
42
43 /*
44  * Hardware Reset Configuration Word
45  * if CLKIN is 66.66MHz, then
46  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
47  * We choose the A type silicon as default, so the core is 400Mhz.
48  */
49 #define CONFIG_SYS_HRCW_LOW (\
50         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
51         HRCWL_DDR_TO_SCB_CLK_2X1 |\
52         HRCWL_SVCOD_DIV_2 |\
53         HRCWL_CSB_TO_CLKIN_4X1 |\
54         HRCWL_CORE_TO_CSB_3X1)
55 /*
56  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
57  * in 8308's HRCWH according to the manual, but original Freescale's
58  * code has them and I've expirienced some problems using the board
59  * with BDI3000 attached when I've tried to set these bits to zero
60  * (UART doesn't work after the 'reset run' command).
61  */
62 #define CONFIG_SYS_HRCW_HIGH (\
63         HRCWH_PCI_HOST |\
64         HRCWH_PCI1_ARBITER_ENABLE |\
65         HRCWH_CORE_ENABLE |\
66         HRCWH_FROM_0XFFF00100 |\
67         HRCWH_BOOTSEQ_DISABLE |\
68         HRCWH_SW_WATCHDOG_DISABLE |\
69         HRCWH_ROM_LOC_LOCAL_16BIT |\
70         HRCWH_RL_EXT_LEGACY |\
71         HRCWH_TSEC1M_IN_MII |\
72         HRCWH_TSEC2M_IN_RGMII |\
73         HRCWH_BIG_ENDIAN)
74
75 /*
76  * System IO Config
77  */
78 #define CONFIG_SYS_SICRH (\
79         SICRH_ESDHC_A_SD |\
80         SICRH_ESDHC_B_SD |\
81         SICRH_ESDHC_C_SD |\
82         SICRH_GPIO_A_GPIO |\
83         SICRH_GPIO_B_GPIO |\
84         SICRH_IEEE1588_A_GPIO |\
85         SICRH_USB |\
86         SICRH_GTM_GPIO |\
87         SICRH_IEEE1588_B_GPIO |\
88         SICRH_ETSEC2_GPIO |\
89         SICRH_GPIOSEL_1 |\
90         SICRH_TMROBI_V3P3 |\
91         SICRH_TSOBI1_V2P5 |\
92         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
93 #define CONFIG_SYS_SICRL (\
94         SICRL_SPI_PF0 |\
95         SICRL_UART_PF0 |\
96         SICRL_IRQ_PF0 |\
97         SICRL_I2C2_PF0 |\
98         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
99
100 /*
101  * IMMR new address
102  */
103 #define CONFIG_SYS_IMMR         0xE0000000
104
105 /*
106  * SERDES
107  */
108 #define CONFIG_FSL_SERDES
109 #define CONFIG_FSL_SERDES1      0xe3000
110
111 /*
112  * Arbiter Setup
113  */
114 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
115 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
116 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
117
118 /*
119  * DDR Setup
120  */
121 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
122 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
123 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
124 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
125 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
126                                 | DDRCDR_PZ_LOZ \
127                                 | DDRCDR_NZ_LOZ \
128                                 | DDRCDR_ODT \
129                                 | DDRCDR_Q_DRN)
130                                 /* 0x7b880001 */
131 /*
132  * Manually set up DDR parameters
133  * consist of one chip NT5TU64M16HG from NANYA
134  */
135
136 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
137
138 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
139 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
140                                 | CSCONFIG_ODT_RD_NEVER \
141                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
142                                 | CSCONFIG_BANK_BIT_3 \
143                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
144                                 /* 0x80010102 */
145 #define CONFIG_SYS_DDR_TIMING_3 0
146 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
147                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
148                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
149                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
150                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
151                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
152                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
153                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
154                                 /* 0x00260802 */
155 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
156                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
157                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
158                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
159                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
160                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
161                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
162                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
163                                 /* 0x26279222 */
164 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
165                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
166                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
167                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
168                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
169                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
170                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
171                                 /* 0x021848c5 */
172 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
173                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
174                                 /* 0x08240100 */
175 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
176                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
177                                 | SDRAM_CFG_DBW_16)
178                                 /* 0x43100000 */
179
180 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
181 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
182                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
183                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
184 #define CONFIG_SYS_DDR_MODE2            0x00000000
185
186 /*
187  * Memory test
188  */
189 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
190 #define CONFIG_SYS_MEMTEST_END          0x07f00000
191
192 /*
193  * The reserved memory
194  */
195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
196
197 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
198 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
199
200 /*
201  * Initial RAM Base Address Setup
202  */
203 #define CONFIG_SYS_INIT_RAM_LOCK        1
204 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
205 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
206 #define CONFIG_SYS_GBL_DATA_OFFSET      \
207         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208
209 /*
210  * Local Bus Configuration & Clock Setup
211  */
212 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
213 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
214 #define CONFIG_SYS_LBC_LBCR             0x00040000
215
216 /*
217  * FLASH on the Local Bus
218  */
219 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
220 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
221 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
222 #define CONFIG_FLASH_CFI_LEGACY
223 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
224
225 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
226 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
227 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
228
229 /* Window base at flash base */
230 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
231 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
232
233 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
234                                 | BR_PS_16      /* 16 bit port */ \
235                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
236                                 | BR_V)         /* valid */
237 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
238                                 | OR_UPM_XAM \
239                                 | OR_GPCM_CSNT \
240                                 | OR_GPCM_ACS_DIV2 \
241                                 | OR_GPCM_XACS \
242                                 | OR_GPCM_SCY_15 \
243                                 | OR_GPCM_TRLX_SET \
244                                 | OR_GPCM_EHTR_SET)
245
246 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
247 #define CONFIG_SYS_MAX_FLASH_SECT       135
248
249 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
250 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
251
252 /*
253  * FPGA
254  */
255 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
256 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
257
258 /* Window base at FPGA base */
259 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
260 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
261
262 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
263                                 | BR_PS_16      /* 16 bit port */ \
264                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
265                                 | BR_V)         /* valid */
266
267 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
268                                 | OR_UPM_XAM \
269                                 | OR_GPCM_CSNT \
270                                 | OR_GPCM_SCY_5 \
271                                 | OR_GPCM_TRLX_CLEAR \
272                                 | OR_GPCM_EHTR_CLEAR)
273
274 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
275 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
276
277 #define CONFIG_SYS_FPGA_COUNT           1
278
279 #define CONFIG_SYS_MCLINK_MAX           3
280
281 #define CONFIG_SYS_FPGA_PTR \
282         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
283
284 #define CONFIG_SYS_FPGA_NO_RFL_HI
285
286 /*
287  * Serial Port
288  */
289 #define CONFIG_CONS_INDEX       2
290 #define CONFIG_SYS_NS16550_SERIAL
291 #define CONFIG_SYS_NS16550_REG_SIZE     1
292 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
293
294 #define CONFIG_SYS_BAUDRATE_TABLE  \
295         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
296
297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
299
300 /* Pass open firmware flat tree */
301
302 /* I2C */
303 #define CONFIG_SYS_I2C
304 #define CONFIG_SYS_I2C_FSL
305 #define CONFIG_SYS_FSL_I2C_SPEED        400000
306 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
307 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
308
309 #define CONFIG_PCA953X                  /* NXP PCA9554 */
310 #define CONFIG_CMD_PCA953X
311 #define CONFIG_CMD_PCA953X_INFO
312 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
313                                           {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
314
315 #define CONFIG_PCA9698                  /* NXP PCA9698 */
316
317 #define CONFIG_SYS_I2C_IHS
318 #define CONFIG_SYS_I2C_IHS_CH0
319 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
320 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
321 #define CONFIG_SYS_I2C_IHS_CH1
322 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
323 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
324 #define CONFIG_SYS_I2C_IHS_CH2
325 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
326 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
327 #define CONFIG_SYS_I2C_IHS_CH3
328 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
329 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
330
331 #ifdef CONFIG_STRIDER_CON_DP
332 #define CONFIG_SYS_I2C_IHS_DUAL
333 #define CONFIG_SYS_I2C_IHS_CH0_1
334 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
335 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
336 #define CONFIG_SYS_I2C_IHS_CH1_1
337 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
338 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
339 #define CONFIG_SYS_I2C_IHS_CH2_1
340 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
341 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
342 #define CONFIG_SYS_I2C_IHS_CH3_1
343 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
344 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
345 #endif
346
347 /*
348  * Software (bit-bang) I2C driver configuration
349  */
350 #define CONFIG_SYS_I2C_SOFT
351 #define CONFIG_SOFT_I2C_READ_REPEATED_START
352 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
353 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
354 #define I2C_SOFT_DECLARATIONS2
355 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
356 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
357 #define I2C_SOFT_DECLARATIONS3
358 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
359 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
360 #define I2C_SOFT_DECLARATIONS4
361 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
362 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
363 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
364 #define I2C_SOFT_DECLARATIONS5
365 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
366 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
367 #define I2C_SOFT_DECLARATIONS6
368 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
369 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
370 #define I2C_SOFT_DECLARATIONS7
371 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
372 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
373 #define I2C_SOFT_DECLARATIONS8
374 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
375 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
376 #endif
377 #ifdef CONFIG_STRIDER_CON_DP
378 #define I2C_SOFT_DECLARATIONS9
379 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
380 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
381 #define I2C_SOFT_DECLARATIONS10
382 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
383 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
384 #define I2C_SOFT_DECLARATIONS11
385 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
386 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
387 #define I2C_SOFT_DECLARATIONS12
388 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
389 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
390 #endif
391
392 #ifdef CONFIG_STRIDER_CON
393 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
394 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
395 #define CONFIG_SYS_ADV7611_I2C                  {5, 6, 7, 8}
396 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
397 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
398                                                   {12, 0x4c} }
399 #elif defined(CONFIG_STRIDER_CON_DP)
400 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
401 #define CONFIG_SYS_CH7301_I2C                   {1, 3, 5, 7}
402 #define CONFIG_SYS_ADV7611_I2C                  {1, 3, 5, 7}
403 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
404 #define CONFIG_STRIDER_FANS                     { {10, 0x4c}, {11, 0x4c}, \
405                                                   {12, 0x4c} }
406 #elif defined(CONFIG_STRIDER_CPU_DP)
407 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
408 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
409 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
410 #define CONFIG_STRIDER_FANS                     { {6, 0x4c}, {7, 0x4c}, \
411                                                   {8, 0x4c} }
412 #else
413 #define CONFIG_SYS_CH7301_I2C                   {1, 2, 3, 4}
414 #define CONFIG_SYS_ADV7611_I2C                  {1, 2, 3, 4}
415 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
416 #define CONFIG_STRIDER_FANS                     { {2, 0x18}, {3, 0x18}, \
417                                                   {4, 0x18} }
418 #endif
419
420 #ifndef __ASSEMBLY__
421 void fpga_gpio_set(unsigned int bus, int pin);
422 void fpga_gpio_clear(unsigned int bus, int pin);
423 int fpga_gpio_get(unsigned int bus, int pin);
424 void fpga_control_set(unsigned int bus, int pin);
425 void fpga_control_clear(unsigned int bus, int pin);
426 #endif
427
428 #ifdef CONFIG_STRIDER_CON
429 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
430 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
431 #define I2C_FPGA_IDX    ((I2C_ADAP_HWNR > 3) ? \
432                          (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
433 #elif defined(CONFIG_STRIDER_CON_DP)
434 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
435 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
436 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
437 #else
438 #define I2C_SDA_GPIO    0x0040
439 #define I2C_SCL_GPIO    0x0020
440 #define I2C_FPGA_IDX    I2C_ADAP_HWNR
441 #endif
442
443 #ifdef CONFIG_STRIDER_CON_DP
444 #define I2C_ACTIVE \
445         do { \
446                 if (I2C_ADAP_HWNR > 7) \
447                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
448                 else \
449                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
450         } while (0)
451 #else
452 #define I2C_ACTIVE      { }
453 #endif
454
455 #define I2C_TRISTATE    { }
456 #define I2C_READ \
457         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
458 #define I2C_SDA(bit) \
459         do { \
460                 if (bit) \
461                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
462                 else \
463                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
464         } while (0)
465 #define I2C_SCL(bit) \
466         do { \
467                 if (bit) \
468                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
469                 else \
470                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
471         } while (0)
472 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
473
474 /*
475  * Software (bit-bang) MII driver configuration
476  */
477 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
478 #define CONFIG_BITBANGMII_MULTI
479
480 /*
481  * OSD Setup
482  */
483 #define CONFIG_SYS_OSD_SCREENS          1
484 #define CONFIG_SYS_DP501_DIFFERENTIAL
485 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
486
487 #ifdef CONFIG_STRIDER_CON_DP
488 #define CONFIG_SYS_OSD_DH
489 #endif
490
491 /*
492  * General PCI
493  * Addresses are mapped 1-1.
494  */
495 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
496 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
497 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
498 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
499 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
500 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
501 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
502 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
503 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
504
505 /* enable PCIE clock */
506 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
507
508 #define CONFIG_PCI_INDIRECT_BRIDGE
509 #define CONFIG_PCIE
510
511 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
512 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
513
514 /*
515  * TSEC
516  */
517 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
518 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
519 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
520
521 /*
522  * TSEC ethernet configuration
523  */
524 #define CONFIG_MII              1 /* MII PHY management */
525 #define CONFIG_TSEC1
526 #define CONFIG_TSEC1_NAME       "eTSEC0"
527 #define TSEC1_PHY_ADDR          1
528 #define TSEC1_PHYIDX            0
529 #define TSEC1_FLAGS             0
530
531 /* Options are: eTSEC[0-1] */
532 #define CONFIG_ETHPRIME         "eTSEC0"
533
534 /*
535  * Environment
536  */
537 #if 1
538 #define CONFIG_ENV_IS_IN_FLASH  1
539 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
540                                  CONFIG_SYS_MONITOR_LEN)
541 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
542 #define CONFIG_ENV_SIZE         0x2000
543 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
544 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
545 #else
546 #define CONFIG_ENV_IS_NOWHERE
547 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
548 #endif
549
550 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
551 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
552
553 /*
554  * Command line configuration.
555  */
556 #define CONFIG_CMD_PCI
557
558 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
559 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
560
561 /*
562  * Miscellaneous configurable options
563  */
564 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
565 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
566 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
567
568 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
569
570 /* Print Buffer Size */
571 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
572 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
573 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
574
575 /*
576  * For booting Linux, the board info and command line data
577  * have to be in the first 256 MB of memory, since this is
578  * the maximum mapped by the Linux kernel during initialization.
579  */
580 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
581
582 /*
583  * Core HID Setup
584  */
585 #define CONFIG_SYS_HID0_INIT    0x000000000
586 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
587                                  HID0_ENABLE_INSTRUCTION_CACHE | \
588                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
589 #define CONFIG_SYS_HID2         HID2_HBE
590
591 /*
592  * MMU Setup
593  */
594
595 /* DDR: cache cacheable */
596 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
597                                         BATL_MEMCOHERENCE)
598 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
599                                         BATU_VS | BATU_VP)
600 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
601 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
602
603 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
604 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
605                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
606 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
607                                         BATU_VP)
608 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
609 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
610
611 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
612 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
613                                         BATL_MEMCOHERENCE)
614 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
615                                         BATU_VS | BATU_VP)
616 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
617                                         BATL_CACHEINHIBIT | \
618                                         BATL_GUARDEDSTORAGE)
619 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
620
621 /* Stack in dcache: cacheable, no memory coherence */
622 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
623 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
624                                         BATU_VS | BATU_VP)
625 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
626 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
627
628 /*
629  * Environment Configuration
630  */
631
632 #define CONFIG_ENV_OVERWRITE
633
634 #if defined(CONFIG_TSEC_ENET)
635 #define CONFIG_HAS_ETH0
636 #endif
637
638 #define CONFIG_BAUDRATE 115200
639
640 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
641
642
643 #define CONFIG_HOSTNAME         hrcon
644 #define CONFIG_ROOTPATH         "/opt/nfsroot"
645 #define CONFIG_BOOTFILE         "uImage"
646
647 #define CONFIG_PREBOOT          /* enable preboot variable */
648
649 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
650         "netdev=eth0\0"                                                 \
651         "consoledev=ttyS1\0"                                            \
652         "u-boot=u-boot.bin\0"                                           \
653         "kernel_addr=1000000\0"                                 \
654         "fdt_addr=C00000\0"                                             \
655         "fdtfile=hrcon.dtb\0"                           \
656         "load=tftp ${loadaddr} ${u-boot}\0"                             \
657         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
658                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
659                 " +${filesize};cp.b ${fileaddr} "                       \
660                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
661         "upd=run load update\0"                                         \
662
663 #define CONFIG_NFSBOOTCOMMAND                                           \
664         "setenv bootargs root=/dev/nfs rw "                             \
665         "nfsroot=$serverip:$rootpath "                                  \
666         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
667         "console=$consoledev,$baudrate $othbootargs;"                   \
668         "tftp ${kernel_addr} $bootfile;"                                \
669         "tftp ${fdt_addr} $fdtfile;"                                    \
670         "bootm ${kernel_addr} - ${fdt_addr}"
671
672 #define CONFIG_MMCBOOTCOMMAND                                           \
673         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
674         "console=$consoledev,$baudrate $othbootargs;"                   \
675         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
676         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
677         "bootm ${kernel_addr} - ${fdt_addr}"
678
679 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
680
681 #endif  /* __CONFIG_H */