1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
15 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
20 * Hardware Reset Configuration Word
21 * if CLKIN is 66.66MHz, then
22 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
23 * We choose the A type silicon as default, so the core is 400Mhz.
25 #define CONFIG_SYS_HRCW_LOW (\
26 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
27 HRCWL_DDR_TO_SCB_CLK_2X1 |\
29 HRCWL_CSB_TO_CLKIN_4X1 |\
30 HRCWL_CORE_TO_CSB_3X1)
32 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
33 * in 8308's HRCWH according to the manual, but original Freescale's
34 * code has them and I've expirienced some problems using the board
35 * with BDI3000 attached when I've tried to set these bits to zero
36 * (UART doesn't work after the 'reset run' command).
38 #define CONFIG_SYS_HRCW_HIGH (\
40 HRCWH_PCI1_ARBITER_ENABLE |\
42 HRCWH_FROM_0XFFF00100 |\
43 HRCWH_BOOTSEQ_DISABLE |\
44 HRCWH_SW_WATCHDOG_DISABLE |\
45 HRCWH_ROM_LOC_LOCAL_16BIT |\
46 HRCWH_RL_EXT_LEGACY |\
47 HRCWH_TSEC1M_IN_MII |\
48 HRCWH_TSEC2M_IN_RGMII |\
54 #define CONFIG_SYS_SICRH (\
60 SICRH_IEEE1588_A_GPIO |\
63 SICRH_IEEE1588_B_GPIO |\
68 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
69 #define CONFIG_SYS_SICRL (\
74 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
79 #define CONFIG_SYS_IMMR 0xE0000000
84 #define CONFIG_FSL_SERDES
85 #define CONFIG_FSL_SERDES1 0xe3000
90 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
91 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
97 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
99 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
100 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
108 * Manually set up DDR parameters
109 * consist of one chip NT5TU64M16HG from NANYA
112 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
114 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
115 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
116 | CSCONFIG_ODT_RD_NEVER \
117 | CSCONFIG_ODT_WR_ONLY_CURRENT \
118 | CSCONFIG_BANK_BIT_3 \
119 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
121 #define CONFIG_SYS_DDR_TIMING_3 0
122 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
123 | (0 << TIMING_CFG0_WRT_SHIFT) \
124 | (0 << TIMING_CFG0_RRT_SHIFT) \
125 | (0 << TIMING_CFG0_WWT_SHIFT) \
126 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
127 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
128 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
129 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
131 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
132 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
133 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
134 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
135 | (9 << TIMING_CFG1_REFREC_SHIFT) \
136 | (2 << TIMING_CFG1_WRREC_SHIFT) \
137 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
138 | (2 << TIMING_CFG1_WRTORD_SHIFT))
140 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
141 | (4 << TIMING_CFG2_CPO_SHIFT) \
142 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
143 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
144 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
145 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
146 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
148 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
149 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
151 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
152 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
156 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
157 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
158 | (0x0242 << SDRAM_MODE_SD_SHIFT))
159 /* ODT 150ohm CL=4, AL=0 on SDRAM */
160 #define CONFIG_SYS_DDR_MODE2 0x00000000
165 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
166 #define CONFIG_SYS_MEMTEST_END 0x07f00000
169 * The reserved memory
171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
173 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
174 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
177 * Initial RAM Base Address Setup
179 #define CONFIG_SYS_INIT_RAM_LOCK 1
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
182 #define CONFIG_SYS_GBL_DATA_OFFSET \
183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 * Local Bus Configuration & Clock Setup
188 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
189 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
190 #define CONFIG_SYS_LBC_LBCR 0x00040000
193 * FLASH on the Local Bus
195 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
196 #define CONFIG_FLASH_CFI_LEGACY
197 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
199 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
200 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
202 /* Window base at flash base */
203 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
206 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
207 | BR_PS_16 /* 16 bit port */ \
208 | BR_MS_GPCM /* MSEL = GPCM */ \
210 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
220 #define CONFIG_SYS_MAX_FLASH_SECT 135
222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
228 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
229 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
231 /* Window base at FPGA base */
232 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
233 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
235 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
236 | BR_PS_16 /* 16 bit port */ \
237 | BR_MS_GPCM /* MSEL = GPCM */ \
240 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
244 | OR_GPCM_TRLX_CLEAR \
245 | OR_GPCM_EHTR_CLEAR)
247 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
248 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
250 #define CONFIG_SYS_FPGA_COUNT 1
252 #define CONFIG_SYS_MCLINK_MAX 3
254 #define CONFIG_SYS_FPGA_PTR \
255 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
257 #define CONFIG_SYS_FPGA_NO_RFL_HI
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
266 #define CONFIG_SYS_BAUDRATE_TABLE \
267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
269 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
270 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
272 /* Pass open firmware flat tree */
275 #define CONFIG_SYS_I2C
276 #define CONFIG_SYS_I2C_FSL
277 #define CONFIG_SYS_FSL_I2C_SPEED 400000
278 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
279 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
281 #define CONFIG_PCA953X /* NXP PCA9554 */
282 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
283 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
285 #define CONFIG_PCA9698 /* NXP PCA9698 */
287 #define CONFIG_SYS_I2C_IHS
288 #define CONFIG_SYS_I2C_IHS_CH0
289 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
290 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
291 #define CONFIG_SYS_I2C_IHS_CH1
292 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
293 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
294 #define CONFIG_SYS_I2C_IHS_CH2
295 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
296 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
297 #define CONFIG_SYS_I2C_IHS_CH3
298 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
299 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
301 #ifdef CONFIG_STRIDER_CON_DP
302 #define CONFIG_SYS_I2C_IHS_DUAL
303 #define CONFIG_SYS_I2C_IHS_CH0_1
304 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
305 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
306 #define CONFIG_SYS_I2C_IHS_CH1_1
307 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
308 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
309 #define CONFIG_SYS_I2C_IHS_CH2_1
310 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
311 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
312 #define CONFIG_SYS_I2C_IHS_CH3_1
313 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
314 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
318 * Software (bit-bang) I2C driver configuration
320 #define CONFIG_SYS_I2C_SOFT
321 #define CONFIG_SOFT_I2C_READ_REPEATED_START
322 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
323 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
324 #define I2C_SOFT_DECLARATIONS2
325 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
326 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
327 #define I2C_SOFT_DECLARATIONS3
328 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
329 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
330 #define I2C_SOFT_DECLARATIONS4
331 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
332 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
333 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
334 #define I2C_SOFT_DECLARATIONS5
335 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
336 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
337 #define I2C_SOFT_DECLARATIONS6
338 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
339 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
340 #define I2C_SOFT_DECLARATIONS7
341 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
342 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
343 #define I2C_SOFT_DECLARATIONS8
344 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
345 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
347 #ifdef CONFIG_STRIDER_CON_DP
348 #define I2C_SOFT_DECLARATIONS9
349 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
350 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
351 #define I2C_SOFT_DECLARATIONS10
352 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
353 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
354 #define I2C_SOFT_DECLARATIONS11
355 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
356 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
357 #define I2C_SOFT_DECLARATIONS12
358 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
359 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
362 #ifdef CONFIG_STRIDER_CON
363 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
364 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
365 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
366 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
367 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
369 #elif defined(CONFIG_STRIDER_CON_DP)
370 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
371 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
372 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
373 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
374 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
376 #elif defined(CONFIG_STRIDER_CPU_DP)
377 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
378 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
379 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
380 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
383 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
384 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
385 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
386 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
391 void fpga_gpio_set(unsigned int bus, int pin);
392 void fpga_gpio_clear(unsigned int bus, int pin);
393 int fpga_gpio_get(unsigned int bus, int pin);
394 void fpga_control_set(unsigned int bus, int pin);
395 void fpga_control_clear(unsigned int bus, int pin);
398 #ifdef CONFIG_STRIDER_CON
399 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
400 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
401 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
402 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
403 #elif defined(CONFIG_STRIDER_CON_DP)
404 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
405 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
406 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
408 #define I2C_SDA_GPIO 0x0040
409 #define I2C_SCL_GPIO 0x0020
410 #define I2C_FPGA_IDX I2C_ADAP_HWNR
413 #ifdef CONFIG_STRIDER_CON_DP
416 if (I2C_ADAP_HWNR > 7) \
417 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
419 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
422 #define I2C_ACTIVE { }
425 #define I2C_TRISTATE { }
427 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
428 #define I2C_SDA(bit) \
431 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
433 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
435 #define I2C_SCL(bit) \
438 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
440 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
442 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
445 * Software (bit-bang) MII driver configuration
447 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
448 #define CONFIG_BITBANGMII_MULTI
453 #define CONFIG_SYS_OSD_SCREENS 1
454 #define CONFIG_SYS_DP501_DIFFERENTIAL
455 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
457 #ifdef CONFIG_STRIDER_CON_DP
458 #define CONFIG_SYS_OSD_DH
463 * Addresses are mapped 1-1.
465 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
466 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
467 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
468 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
469 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
470 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
471 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
472 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
473 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
475 /* enable PCIE clock */
476 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
478 #define CONFIG_PCI_INDIRECT_BRIDGE
481 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
482 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
487 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
488 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
491 * TSEC ethernet configuration
494 #define CONFIG_TSEC1_NAME "eTSEC0"
495 #define TSEC1_PHY_ADDR 1
496 #define TSEC1_PHYIDX 0
497 #define TSEC1_FLAGS 0
499 /* Options are: eTSEC[0-1] */
500 #define CONFIG_ETHPRIME "eTSEC0"
506 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
507 CONFIG_SYS_MONITOR_LEN)
508 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
509 #define CONFIG_ENV_SIZE 0x2000
510 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
511 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
513 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
516 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
517 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
520 * Command line configuration.
524 * Miscellaneous configurable options
526 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
527 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
531 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
534 * For booting Linux, the board info and command line data
535 * have to be in the first 256 MB of memory, since this is
536 * the maximum mapped by the Linux kernel during initialization.
538 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
543 #define CONFIG_SYS_HID0_INIT 0x000000000
544 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
545 HID0_ENABLE_INSTRUCTION_CACHE | \
546 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
547 #define CONFIG_SYS_HID2 HID2_HBE
553 /* DDR: cache cacheable */
554 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
556 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
558 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
559 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
561 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
562 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
563 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
564 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
566 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
567 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
569 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
570 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
572 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
574 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
575 BATL_CACHEINHIBIT | \
577 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
579 /* Stack in dcache: cacheable, no memory coherence */
580 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
581 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
583 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
584 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
587 * Environment Configuration
590 #define CONFIG_ENV_OVERWRITE
592 #if defined(CONFIG_TSEC_ENET)
593 #define CONFIG_HAS_ETH0
596 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
599 #define CONFIG_HOSTNAME "hrcon"
600 #define CONFIG_ROOTPATH "/opt/nfsroot"
601 #define CONFIG_BOOTFILE "uImage"
603 #define CONFIG_PREBOOT /* enable preboot variable */
605 #define CONFIG_EXTRA_ENV_SETTINGS \
607 "consoledev=ttyS1\0" \
608 "u-boot=u-boot.bin\0" \
609 "kernel_addr=1000000\0" \
610 "fdt_addr=C00000\0" \
611 "fdtfile=hrcon.dtb\0" \
612 "load=tftp ${loadaddr} ${u-boot}\0" \
613 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
614 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
615 " +${filesize};cp.b ${fileaddr} " \
616 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
617 "upd=run load update\0" \
619 #define CONFIG_NFSBOOTCOMMAND \
620 "setenv bootargs root=/dev/nfs rw " \
621 "nfsroot=$serverip:$rootpath " \
622 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
623 "console=$consoledev,$baudrate $othbootargs;" \
624 "tftp ${kernel_addr} $bootfile;" \
625 "tftp ${fdt_addr} $fdtfile;" \
626 "bootm ${kernel_addr} - ${fdt_addr}"
628 #define CONFIG_MMCBOOTCOMMAND \
629 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
630 "console=$consoledev,$baudrate $othbootargs;" \
631 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
632 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
633 "bootm ${kernel_addr} - ${fdt_addr}"
635 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
637 #endif /* __CONFIG_H */