1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Sysam stmark2 board configuration
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
8 #ifndef __STMARK2_CONFIG_H
9 #define __STMARK2_CONFIG_H
11 #define CONFIG_HOSTNAME "stmark2"
13 #define CONFIG_MCFUART
14 #define CONFIG_SYS_UART_PORT 0
15 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
17 #define LDS_BOARD_TEXT \
18 board/sysam/stmark2/sbf_dram_init.o (.text*)
20 #define CONFIG_TIMESTAMP
22 #define CONFIG_BOOTARGS \
23 "console=ttyS0,115200 root=/dev/ram0 rw " \
28 #define CONFIG_BOOTCOMMAND \
29 "sf probe 0:1 50000000; " \
30 "sf read ${loadaddr} 0x100000 ${kern_size}; " \
33 #define CONFIG_EXTRA_ENV_SETTINGS \
34 "kern_size=0x700000\0" \
35 "loadaddr=0x40001000\0" \
37 "update_uboot=loady ${loadaddr}; " \
38 "sf probe 0:1 50000000; " \
39 "sf erase 0 0x80000; " \
40 "sf write ${loadaddr} 0 ${filesize}\0" \
41 "update_kernel=loady ${loadaddr}; " \
42 "setenv kern_size ${filesize}; saveenv; " \
43 "sf probe 0:1 50000000; " \
44 "sf erase 0x100000 0x700000; " \
45 "sf write ${loadaddr} 0x100000 ${filesize}\0" \
46 "update_rootfs=loady ${loadaddr}; " \
47 "sf probe 0:1 50000000; " \
48 "sf erase 0x00800000 0x100000; " \
49 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
54 #define CONFIG_RTC_MCFRRTC
55 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
57 /* spi not partitions */
58 #define CONFIG_JFFS2_CMDLINE
59 #define CONFIG_JFFS2_DEV "nor0"
64 /* DSPI and Serial Flash */
65 #define CONFIG_CF_DSPI
66 #define CONFIG_SERIAL_FLASH
68 #define CONFIG_SYS_SBFHDR_SIZE 0x7
70 /* Input, PCI, Flexbus, and VCO */
71 #define CONFIG_EXTRA_CLOCK
73 #define CONFIG_PRAM 2048 /* 2048 KB */
74 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
76 /* Print Buffer Size */
77 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
78 sizeof(CONFIG_SYS_PROMPT) + 16)
79 #define CONFIG_SYS_MAXARGS 16
80 /* Boot Argument Buffer Size */
81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
83 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
84 #define CONFIG_SYS_MBAR 0xFC000000
87 * Definitions for initial stack pointer and data area (in internal SRAM)
89 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
90 /* End of used area in internal SRAM */
91 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
92 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
93 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
94 GENERATED_GBL_DATA_SIZE) - 32)
95 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
96 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
99 * Start addresses for the final memory configuration
100 * (Set up by the startup code)
101 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
103 #define CONFIG_SYS_SDRAM_BASE 0x40000000
104 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
106 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
107 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
108 #define CONFIG_SYS_DRAM_TEST
110 #if defined(CONFIG_CF_SBF)
111 #define CONFIG_SERIAL_BOOT
114 #if defined(CONFIG_SERIAL_BOOT)
115 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
117 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
120 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
121 /* Reserve 256 kB for Monitor */
122 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
123 /* Reserve 256 kB for malloc() */
124 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
127 * For booting Linux, the board info and command line data
128 * have to be in the first 8 MB of memory, since this is
129 * the maximum mapped by the Linux kernel during initialization ??
131 /* Initial Memory map for Linux */
132 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
133 (CONFIG_SYS_SDRAM_SIZE << 20))
135 /* Configuration for environment
136 * Environment is embedded in u-boot in the second sector of the flash
139 #if defined(CONFIG_CF_SBF)
140 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
143 #undef CONFIG_ENV_OVERWRITE
145 /* Cache Configuration */
146 #define CONFIG_SYS_CACHELINE_SIZE 16
147 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
148 CONFIG_SYS_INIT_RAM_SIZE - 8)
149 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
150 CONFIG_SYS_INIT_RAM_SIZE - 4)
151 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
152 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
153 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
154 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
155 CF_ACR_EN | CF_ACR_SM_ALL)
156 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
157 CF_CACR_ICINVA | CF_CACR_EUSP)
158 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
159 CF_CACR_DEC | CF_CACR_DDCM_P | \
160 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
162 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
163 CONFIG_SYS_INIT_RAM_SIZE - 12)
166 #define CONFIG_MII_INIT 1
167 #define CONFIG_SYS_DISCOVER_PHY
168 #define CONFIG_SYS_RX_ETH_BUFFER 8
169 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
170 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
171 #ifndef CONFIG_SYS_DISCOVER_PHY
172 #define FECDUPLEX FULL
173 #define FECSPEED _100BASET
175 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
176 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
178 #endif /* CONFIG_SYS_DISCOVER_PHY */
180 #endif /* __STMARK2_CONFIG_H */