3 * Kamil Lulko, <kamil.lulko@gmail.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_STM32F4DISCOVERY
13 #define CONFIG_MISC_INIT_R
15 #define CONFIG_SYS_FLASH_BASE 0x08000000
17 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
18 #define CONFIG_SYS_TEXT_BASE 0x08000000
20 #define CONFIG_SYS_ICACHE_OFF
21 #define CONFIG_SYS_DCACHE_OFF
24 * Configuration of the external SDRAM memory
26 #define CONFIG_NR_DRAM_BANKS 1
27 #define CONFIG_SYS_RAM_SIZE (8 << 20)
28 #define CONFIG_SYS_RAM_CS 1
29 #define CONFIG_SYS_RAM_FREQ_DIV 2
30 #define CONFIG_SYS_RAM_BASE 0xD0000000
31 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
32 #define CONFIG_SYS_LOAD_ADDR 0xD0400000
33 #define CONFIG_LOADADDR 0xD0400000
35 #define CONFIG_SYS_MAX_FLASH_SECT 12
36 #define CONFIG_SYS_MAX_FLASH_BANKS 2
38 #define CONFIG_ENV_OFFSET (256 << 10)
39 #define CONFIG_ENV_SECT_SIZE (128 << 10)
40 #define CONFIG_ENV_SIZE (8 << 10)
42 #define CONFIG_RED_LED 110
43 #define CONFIG_GREEN_LED 109
45 #define CONFIG_STM32_GPIO
46 #define CONFIG_STM32_FLASH
47 #define CONFIG_STM32_SERIAL
49 #define CONFIG_STM32_HSE_HZ 8000000
51 #define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
53 #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
55 #define CONFIG_CMDLINE_TAG
56 #define CONFIG_SETUP_MEMORY_TAGS
57 #define CONFIG_INITRD_TAG
58 #define CONFIG_REVISION_TAG
60 #define CONFIG_SYS_CBSIZE 1024
61 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
62 + sizeof(CONFIG_SYS_PROMPT) + 16)
64 #define CONFIG_SYS_MAXARGS 16
66 #define CONFIG_SYS_MALLOC_LEN (2 << 20)
68 #define CONFIG_BOOTCOMMAND \
71 #define CONFIG_EXTRA_ENV_SETTINGS \
72 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
73 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
74 "bootm 0x08044000 - 0x08042000\0"
77 * Command line configuration.
79 #define CONFIG_SYS_LONGHELP
80 #define CONFIG_AUTO_COMPLETE
81 #define CONFIG_CMDLINE_EDITING
83 #endif /* __CONFIG_H */