3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _SPEAR_COMMON_H
9 #define _SPEAR_COMMON_H
11 * Common configurations used for both spear3xx as well as spear6xx
14 /* U-Boot Load Address */
15 #define CONFIG_SYS_TEXT_BASE 0x00700000
17 /* Ethernet driver configuration */
19 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
21 /* USBD driver configuration */
22 #if defined(CONFIG_SPEAR_USBTTY)
24 #define CONFIG_USB_DEVICE
25 #define CONFIG_USBD_HS
26 #define CONFIG_USB_TTY
28 #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
29 #define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
33 #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
35 /* I2C driver configuration */
36 #define CONFIG_SYS_I2C
37 #if defined(CONFIG_SPEAR600)
38 #define CONFIG_SYS_I2C_BASE 0xD0200000
39 #elif defined(CONFIG_SPEAR300)
40 #define CONFIG_SYS_I2C_BASE 0xD0180000
41 #elif defined(CONFIG_SPEAR310)
42 #define CONFIG_SYS_I2C_BASE 0xD0180000
43 #elif defined(CONFIG_SPEAR320)
44 #define CONFIG_SYS_I2C_BASE 0xD0180000
46 #define CONFIG_SYS_I2C_SPEED 400000
47 #define CONFIG_SYS_I2C_SLAVE 0x02
49 #define CONFIG_I2C_CHIPADDRESS 0x50
51 /* Timer, HZ specific defines */
53 /* Flash configuration */
54 #if defined(CONFIG_FLASH_PNOR)
55 #define CONFIG_SPEAR_EMI
60 #if defined(CONFIG_ST_SMI)
62 #define CONFIG_SYS_MAX_FLASH_BANKS 2
63 #define CONFIG_SYS_FLASH_BASE 0xF8000000
64 #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
65 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
66 #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
67 CONFIG_SYS_CS1_FLASH_BASE}
68 #define CONFIG_SYS_MAX_FLASH_SECT 128
70 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
71 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
76 * Serial Configuration (PL011)
77 * CONFIG_PL01x_PORTS is defined in specific files
79 #define CONFIG_PL011_SERIAL
80 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
81 #define CONFIG_CONS_INDEX 0
82 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
85 #define CONFIG_SYS_LOADS_BAUD_CHANGE
87 /* NAND FLASH Configuration */
88 #define CONFIG_SYS_NAND_SELF_INIT
89 #define CONFIG_MTD_DEVICE
90 #define CONFIG_MTD_PARTITIONS
91 #define CONFIG_NAND_FSMC
92 #define CONFIG_SYS_MAX_NAND_DEVICE 1
93 #define CONFIG_SYS_NAND_ONFI_DETECTION
96 * Command support defines
98 #define CONFIG_CMD_SAVES
101 * Default Environment Varible definitions
103 #define CONFIG_ENV_OVERWRITE
106 * U-Boot Environment placing definitions.
108 #if defined(CONFIG_ENV_IS_IN_FLASH)
111 * Environment is in serial NOR flash
113 #define CONFIG_SYS_MONITOR_LEN 0x00040000
114 #define CONFIG_ENV_SECT_SIZE 0x00010000
115 #define CONFIG_FSMTDBLK "/dev/mtdblock3 "
117 #define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
119 #elif defined(CONFIG_SPEAR_EMI)
121 * Environment is in parallel NOR flash
123 #define CONFIG_SYS_MONITOR_LEN 0x00060000
124 #define CONFIG_ENV_SECT_SIZE 0x00020000
125 #define CONFIG_FSMTDBLK "/dev/mtdblock3 "
127 #define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
128 "0x4C0000; bootm 0x1600000"
131 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
132 CONFIG_SYS_MONITOR_LEN)
133 #elif defined(CONFIG_ENV_IS_IN_NAND)
135 * Environment is in NAND
138 #define CONFIG_ENV_OFFSET 0x60000
139 #define CONFIG_ENV_RANGE 0x10000
140 #define CONFIG_FSMTDBLK "/dev/mtdblock7 "
142 #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
143 "0x80000 0x4C0000; " \
147 #define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
149 "root="CONFIG_FSMTDBLK \
152 #define CONFIG_NFSBOOTCOMMAND \
154 "setenv bootargs root=/dev/nfs rw " \
155 "nfsroot=$(serverip):$(rootpath) " \
156 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
157 "$(netmask):$(hostname):$(netdev):off " \
158 "console=ttyAMA0,115200 $(othbootargs);" \
161 #define CONFIG_RAMBOOTCOMMAND \
162 "setenv bootargs root=/dev/ram rw " \
163 "console=ttyAMA0,115200 $(othbootargs);" \
166 #define CONFIG_ENV_SIZE 0x02000
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169 /* Miscellaneous configurable options */
170 #define CONFIG_ARCH_CPU_INIT
171 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
172 #define CONFIG_CMDLINE_TAG
173 #define CONFIG_SETUP_MEMORY_TAGS
174 #define CONFIG_MISC_INIT_R
176 #define CONFIG_SYS_MEMTEST_START 0x00800000
177 #define CONFIG_SYS_MEMTEST_END 0x04000000
178 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
179 #define CONFIG_SYS_LONGHELP
180 #define CONFIG_CMDLINE_EDITING
181 #define CONFIG_SYS_CBSIZE 256
182 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
183 sizeof(CONFIG_SYS_PROMPT) + 16)
184 #define CONFIG_SYS_MAXARGS 16
185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
186 #define CONFIG_SYS_LOAD_ADDR 0x00800000
188 #define CONFIG_SYS_FLASH_EMPTY_INFO
190 /* Physical Memory Map */
191 #define CONFIG_NR_DRAM_BANKS 1
192 #define PHYS_SDRAM_1 0x00000000
193 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
195 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
196 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
197 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000
199 #define CONFIG_SYS_INIT_SP_OFFSET \
200 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_INIT_SP_ADDR \
203 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)