1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
7 #ifndef _SPEAR_COMMON_H
8 #define _SPEAR_COMMON_H
10 * Common configurations used for both spear3xx as well as spear6xx
13 /* U-Boot Load Address */
15 /* Ethernet driver configuration */
16 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
18 /* USBD driver configuration */
19 #if defined(CONFIG_SPEAR_USBTTY)
21 #define CONFIG_USB_DEVICE
22 #define CONFIG_USBD_HS
23 #define CONFIG_USB_TTY
25 #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
26 #define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
30 #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
32 /* I2C driver configuration */
33 #define CONFIG_SYS_I2C
34 #if defined(CONFIG_SPEAR600)
35 #define CONFIG_SYS_I2C_BASE 0xD0200000
36 #elif defined(CONFIG_SPEAR300)
37 #define CONFIG_SYS_I2C_BASE 0xD0180000
38 #elif defined(CONFIG_SPEAR310)
39 #define CONFIG_SYS_I2C_BASE 0xD0180000
40 #elif defined(CONFIG_SPEAR320)
41 #define CONFIG_SYS_I2C_BASE 0xD0180000
43 #define CONFIG_SYS_I2C_SPEED 400000
44 #define CONFIG_SYS_I2C_SLAVE 0x02
46 #define CONFIG_I2C_CHIPADDRESS 0x50
48 /* Timer, HZ specific defines */
50 /* Flash configuration */
51 #if defined(CONFIG_FLASH_PNOR)
52 #define CONFIG_SPEAR_EMI
57 #if defined(CONFIG_ST_SMI)
59 #define CONFIG_SYS_MAX_FLASH_BANKS 2
60 #define CONFIG_SYS_FLASH_BASE 0xF8000000
61 #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
62 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
63 #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
64 CONFIG_SYS_CS1_FLASH_BASE}
65 #define CONFIG_SYS_MAX_FLASH_SECT 128
67 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
68 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
73 * Serial Configuration (PL011)
74 * CONFIG_PL01x_PORTS is defined in specific files
76 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
77 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
80 #define CONFIG_SYS_LOADS_BAUD_CHANGE
82 /* NAND FLASH Configuration */
83 #define CONFIG_SYS_NAND_SELF_INIT
84 #define CONFIG_NAND_FSMC
85 #define CONFIG_SYS_MAX_NAND_DEVICE 1
86 #define CONFIG_SYS_NAND_ONFI_DETECTION
89 * Default Environment Varible definitions
91 #define CONFIG_ENV_OVERWRITE
94 * U-Boot Environment placing definitions.
96 #if defined(CONFIG_ENV_IS_IN_FLASH)
99 * Environment is in serial NOR flash
101 #define CONFIG_SYS_MONITOR_LEN 0x00040000
102 #define CONFIG_ENV_SECT_SIZE 0x00010000
103 #define CONFIG_FSMTDBLK "/dev/mtdblock3 "
105 #define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
107 #elif defined(CONFIG_SPEAR_EMI)
109 * Environment is in parallel NOR flash
111 #define CONFIG_SYS_MONITOR_LEN 0x00060000
112 #define CONFIG_ENV_SECT_SIZE 0x00020000
113 #define CONFIG_FSMTDBLK "/dev/mtdblock3 "
115 #define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
116 "0x4C0000; bootm 0x1600000"
119 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
120 CONFIG_SYS_MONITOR_LEN)
121 #elif defined(CONFIG_ENV_IS_IN_NAND)
123 * Environment is in NAND
126 #define CONFIG_ENV_OFFSET 0x60000
127 #define CONFIG_ENV_RANGE 0x10000
128 #define CONFIG_FSMTDBLK "/dev/mtdblock7 "
130 #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
131 "0x80000 0x4C0000; " \
135 #define CONFIG_NFSBOOTCOMMAND \
137 "setenv bootargs root=/dev/nfs rw " \
138 "nfsroot=$(serverip):$(rootpath) " \
139 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
140 "$(netmask):$(hostname):$(netdev):off " \
141 "console=ttyAMA0,115200 $(othbootargs);" \
144 #define CONFIG_RAMBOOTCOMMAND \
145 "setenv bootargs root=/dev/ram rw " \
146 "console=ttyAMA0,115200 $(othbootargs);" \
149 #define CONFIG_ENV_SIZE 0x02000
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
152 /* Miscellaneous configurable options */
153 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
154 #define CONFIG_CMDLINE_TAG
155 #define CONFIG_SETUP_MEMORY_TAGS
157 #define CONFIG_SYS_MEMTEST_START 0x00800000
158 #define CONFIG_SYS_MEMTEST_END 0x04000000
159 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
160 #define CONFIG_SYS_LOAD_ADDR 0x00800000
162 #define CONFIG_SYS_FLASH_EMPTY_INFO
164 /* Physical Memory Map */
165 #define PHYS_SDRAM_1 0x00000000
166 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
168 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
169 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000
172 #define CONFIG_SYS_INIT_SP_OFFSET \
173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175 #define CONFIG_SYS_INIT_SP_ADDR \
176 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)