2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #define DT_PLATFROM_ID 8830
25 #define DT_HARDWARE_ID 1
26 #define DT_SOC_VER 0x20000
28 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
29 #define CONFIG_FDL2_PRINT 0
30 #define BOOT_NATIVE_LINUX 1
31 #define BOOT_NATIVE_LINUX_MODEM 1
32 #define CONFIG_SILENT_CONSOLE
33 #define CONFIG_GPIOLIB 1
36 #define CONFIG_SDRAMDISK
38 #define U_BOOT_SPRD_VER 1
39 /*#define SPRD_EVM_TAG_ON 1*/
40 #ifdef SPRD_EVM_TAG_ON
41 #define SPRD_EVM_ADDR_START 0x00026000
42 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
44 #define CONFIG_L2_OFF 1
48 #define CONFIG_YAFFS2 1
50 #define BOOT_PART "boot"
51 //#define BOOT_PART "kernel"
52 #define RECOVERY_PART "recovery"
54 * SPREADTRUM BIGPHONE board - SoC Configuration
56 #define CONFIG_AUTODLOADER
57 #define CONFIG_SP9820FPGA
60 #define CONFIG_ADIE_SC2723
62 #define CONFIG_SPL_32K
64 #define CONFIG_SUPPORT_TDLTE
65 #define TDDSP_ADR 0x88020000
66 //#define CONFIG_SUPPORT_WLTE
67 #define CONFIG_SUPPORT_GSM
69 #define LTE_GDSP_LOAD_OFFSET 0x20000
71 #define LTE_FIXNV_SIZE 0x00040000 //128k==>256k
72 #define LTE_RUNNV_SIZE 0x00060000 // 256K==>384K
73 #define LTE_FIXNV_ADDR 0x8b6d0000 //0x8a310000
74 #define LTE_RUNNV_ADDR 0x8b710000 //0x8a330000
75 #define LTE_MODEM_SIZE 0x008b0000 //0x8f0000
76 #define LTE_MODEM_ADDR 0x8ae00000
77 #define LTE_LDSP_SIZE 0x00b00000
78 #define LTE_LDSP_ADDR 0x89900000
79 #define LTE_GDSP_SIZE 0x002E0000
80 #define LTE_GDSP_ADDR (0x89600000 + LTE_GDSP_LOAD_OFFSET)
82 #define WL_WARM_SIZE 0x670000
83 #define WL_WARM_ADDR 0X88400000
85 #define GSM_FIXNV_SIZE 0x20000
86 #define GSM_FIXNV_ADDR 0x88a90000
87 #define GSM_RUNNV_SIZE 0x40000
88 #define GSM_RUNNV_ADDR 0x88ab0000
89 #define GSM_MODEM_ADDR 0X88400000 //equal to WL_DSDA_WARM_ADDR
90 #define GSM_MODEM_SIZE 0x670000 //equal to WL_DSDA_WARM_SIZE
91 #define GSM_DSP_ADDR 0x88000000
92 #define GSM_DSP_SIZE 0x400000
93 #define FIXNV_SIZE LTE_FIXNV_SIZE
95 #define CONFIG_DFS_ENABLE
96 #define DFS_ADDR 0x50800000
97 #define DFS_SIZE 32768 //32K
99 //#define CONFIG_CP0_ARM0_BOOT
100 #define CONFIG_PMIC_ARM7_BOOT
101 #define CONFIG_CP1_BOOT
102 #define CHIP_ENDIAN_LITTLE
103 #define _LITTLE_ENDIAN 1
105 #define CONFIG_RAM512M
107 #define CONFIG_EMMC_BOOT
108 #define CONFIG_ARCH_SCX35L
109 #define CONFIG_ARCH_SCX20L
111 #ifdef CONFIG_EMMC_BOOT
112 #define EMMC_SECTOR_SIZE 512
114 #define CONFIG_FS_EXT4
115 #define CONFIG_EXT4_WRITE
116 #define CONFIG_CMD_EXT4
117 #define CONFIG_CMD_EXT4_WRITE
119 //#define CONFIG_TIGER_MMC
120 #define CONFIG_UEFI_PARTITION
121 #define CONFIG_EXT4_SPARSE_DOWNLOAD
122 //#define CONFIG_EMMC_SPL
123 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
129 #define CONFIG_CMD_MMC
130 #ifdef CONFIG_CMD_MMC
131 #define CONFIG_CMD_FAT 1
132 #define CONFIG_FAT_WRITE 1
134 #define CONFIG_GENERIC_MMC 1
135 #define CONFIG_SDHCI 1
136 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
137 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
138 #define CONFIG_MMC_SDMA 1
139 #define CONFIG_MV_SDHCI 1
140 #define CONFIG_DOS_PARTITION 1
141 #define CONFIG_EFI_PARTITION 1
142 #define CONFIG_SYS_MMC_NUM 1
145 #define BB_DRAM_TYPE_256MB_32BIT
147 #define CONFIG_SYS_HZ 1000
148 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
150 #define CP0_ZERO_MAP_ADR 0x50000000
151 #define CP0_ARM0_EXEC_ADR 0x88400000
153 #define CP1_ZERO_MAP_ADR 0x50001000
154 #define CP1_EXEC_ADR 0x8ae00000
156 #ifdef CONFIG_SYS_HUSH_PARSER
157 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
160 #define PRODUCTINFO_SIZE (16 * 1024)
161 #define MODEM_SIZE (0x800000)
162 #define DSP_SIZE (0x2E0000)
163 #define VMJALUNA_SIZE (0x64000) /* 400K */
164 #define RUNTIMENV_SIZE (3*128 * 1024)
165 #define CONFIG_SPL_LOAD_LEN (0x6000)
168 /*#define CMDLINE_NEED_CONV */
170 #define WATCHDOG_LOAD_VALUE 0x4000
171 #define CONFIG_SYS_STACK_SIZE 0x400
172 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
174 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
176 /* NAND BOOT is the only boot method */
177 #define CONFIG_NAND_U_BOOT
178 #define DYNAMIC_CRC_TABLE
179 /* Start copying real U-boot from the second page */
180 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
181 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
182 #define RAM_TYPPE_IS_SDRAM 0
183 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
185 /* Load U-Boot to this address */
186 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
187 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
188 #define CONFIG_SYS_SDRAM_BASE 0x80000000
189 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
191 #ifdef CONFIG_NAND_SPL
192 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
195 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
196 #define CONFIG_SYS_INIT_SP_ADDR \
197 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
199 #define CONFIG_SKIP_LOWLEVEL_INIT
202 #define CONFIG_HW_WATCHDOG
203 #define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
204 //#define CONFIG_DISPLAY_CPUINFO
206 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
207 #define CONFIG_SETUP_MEMORY_TAGS 1
208 #define CONFIG_INITRD_TAG 1
214 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
216 * Board has 2 32MB banks of DRAM but there is a bug when using
217 * both so only the first is configured
219 #define CONFIG_NR_DRAM_BANKS 1
221 #define PHYS_SDRAM_1 0x80000000
222 #define PHYS_SDRAM_1_SIZE 0x10000000
223 #if (CONFIG_NR_DRAM_BANKS == 2)
224 #define PHYS_SDRAM_2 0x90000000
225 #define PHYS_SDRAM_2_SIZE 0x10000000
228 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
229 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
230 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
235 #define CONFIG_SPRD_UART 1
236 #define CONFIG_SYS_SC8800X_UART1 1
237 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
238 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
239 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
240 #define CONFIG_SPRD_SPI
241 #define CONFIG_SPRD_I2C
242 #define CONFIG_SC9630_I2C
244 * Flash & Environment
246 /* No NOR flash present */
247 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
248 #define CONFIG_SYS_NO_FLASH 1
249 #define CONFIG_ENV_IS_NOWHERE
250 #define CONFIG_ENV_SIZE (128 * 1024)
252 #define CONFIG_ENV_IS_IN_NAND
253 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
254 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
259 //---these three macro below,only one can be open
264 //#define DDR_AUTO_DETECT
265 #define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
266 //#define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
267 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
268 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
269 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
270 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
272 #define DDR3_DLL_ON TRUE
274 #define DDR_APB_CLK 128
275 #define DDR_DFS_SUPPORT
276 #define DDR_DFS_VAL_BASE 0X1c00
278 //#define DDR_SCAN_SUPPORT
279 #define MEM_IO_DS LPDDR2_DS_40R
281 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
282 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
283 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
286 #define CONFIG_NAND_SC9630
287 #define CONFIG_SPRD_NAND_REGS_BASE (0x21100000)
288 #define CONFIG_SYS_MAX_NAND_DEVICE 1
289 #define CONFIG_SYS_NAND_BASE (0x21100000)
290 //#define CONFIG_JFFS2_NAND
291 //#define CONFIG_SPRD_NAND_HWECC
292 #define CONFIG_SYS_NAND_HW_ECC
293 #define CONFIG_SYS_NAND_LARGEPAGE
294 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
296 #define CONFIG_SYS_64BIT_VSPRINTF
298 #define CONFIG_CMD_MTDPARTS
299 #define CONFIG_MTD_PARTITIONS
300 #define CONFIG_MTD_DEVICE
301 #define CONFIG_CMD_UBI
302 #define CONFIG_RBTREE
304 /* U-Boot general configuration */
305 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
306 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
307 /* Print buffer sz */
308 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
309 sizeof(CONFIG_SYS_PROMPT) + 16)
310 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
311 /* Boot Argument Buffer Size */
312 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
313 #define CONFIG_CMDLINE_EDITING
314 #define CONFIG_SYS_LONGHELP
316 /* support OS choose */
317 #undef CONFIG_BOOTM_NETBSD
318 #undef CONFIG_BOOTM_RTEMS
320 /* U-Boot commands */
321 #include <config_cmd_default.h>
322 #define CONFIG_CMD_NAND
323 #undef CONFIG_CMD_FPGA
324 #undef CONFIG_CMD_LOADS
325 #undef CONFIG_CMD_NET
326 #undef CONFIG_CMD_NFS
327 #undef CONFIG_CMD_SETGETDCR
329 #define CONFIG_ENV_OVERWRITE
331 #ifdef SPRD_EVM_TAG_ON
332 #define CONFIG_BOOTDELAY 0
334 #define CONFIG_BOOTDELAY 0
335 #define CONFIG_ZERO_BOOTDELAY_CHECK
338 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
339 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
341 #define xstr(s) str(s)
344 #define MTDIDS_DEFAULT "nand0=sprd-nand"
345 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
346 #define CONFIG_BOOTARGS "mem=512M loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
348 #define COPY_LINUX_KERNEL_SIZE (0x600000)
349 #define LINUX_INITRD_NAME "modem"
351 #define CONFIG_BOOTCOMMAND "cboot normal"
352 #define CONFIG_EXTRA_ENV_SETTINGS ""
354 #ifdef CONFIG_CMD_NET
355 #define CONFIG_IPADDR 192.168.10.2
356 #define CONFIG_SERVERIP 192.168.10.5
357 #define CONFIG_NETMASK 255.255.255.0
358 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
359 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
362 #define CONFIG_NET_MULTI
363 #define CONFIG_CMD_DNS
364 #define CONFIG_CMD_NFS
365 #define CONFIG_CMD_RARP
366 #define CONFIG_CMD_PING
367 /*#define CONFIG_CMD_SNTP */
370 #define CONFIG_USB_CORE_IP_293A
371 #define CONFIG_USB_GADGET_SC8800G
372 #define CONFIG_USB_DWC
373 #define CONFIG_USB_GADGET_DUALSPEED
374 //#define CONFIG_USB_ETHER
375 #define CONFIG_CMD_FASTBOOT
376 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
377 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
378 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
379 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
380 #define CONFIG_MODEM_CALIBERATE
384 #define CONFIG_DSIH_VERSION_1P21A
385 #define CONFIG_SPLASH_SCREEN
386 #define LCD_BPP LCD_COLOR16
387 #define CONFIG_LCD_WVGA 1
388 //#define CONFIG_LCD_HVGA 1
389 //#define CONFIG_LCD_QVGA 1
390 //#define CONFIG_LCD_QHD 1
391 //#define CONFIG_LCD_720P 1
392 //#define CONFIG_LCD_INFO
393 //#define LCD_TEST_PATTERN
394 //#define CONFIG_LCD_LOGO
395 //#define CONFIG_FB_LCD_S6D0139
396 #define CONFIG_FB_LCD_RM68180_MIPI
397 #define CONFIG_FB_LCD_NT35516_MIPI
398 #define CONFIG_FB_LCD_ILI9806E_MIPI
399 #define CONFIG_SYS_WHITE_ON_BLACK
400 #ifdef LCD_TEST_PATTERN
401 #define CONSOLE_COLOR_RED 0xf800
402 #define CONSOLE_COLOR_GREEN 0x07e0
403 #define CONSOLE_COLOR_YELLOW 0x07e0
404 #define CONSOLE_COLOR_BLUE 0x001f
405 #define CONSOLE_COLOR_MAGENTA 0x001f
406 #define CONSOLE_COLOR_CYAN 0x001f
410 #define CONFIG_SPRD_SYSDUMP
411 #include <asm/sizes.h>
412 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
415 #define CALIBRATE_ENUM_MS 3000
416 #define CALIBRATE_IO_MS 2000
418 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
419 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
420 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
422 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
423 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
425 #define PHYS_OFFSET_ADDR 0x80000000
426 //#define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
427 //#define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
428 //#define WCDMA_CP_OFFSET_ADDR 0x10000000 /*256M*/
429 //#define WCDMA_CP_SDRAM_SIZE 0x4000000 /*64M*/
430 #define GGE_CP_OFFSET_ADDR 0x08000000 /*128M*/
431 #define GGE_CP_SDRAM_SIZE 0x01600000 /*22M*/
432 #define LTE_CP_OFFSET_ADDR 0x09600000 /*150M*/
433 #define LTE_CP_SDRAM_SIZE 0x04000000 /*64M*/
434 #define PMIC_IRAM_ADDR 0x50800000 /*pmic arm7 iram address remap at AP side*/
435 #define PMIC_IRAM_SIZE 0x8000 /*32K*/
436 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
437 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
438 #define CALIBRATION_CMDLINE_SIZE 0x400 /*1K*/
439 //#define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
440 //#define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x93FFF000*/
441 #define SIPC_GGE_APCP_START_ADDR (PHYS_OFFSET_ADDR + GGE_CP_OFFSET_ADDR + GGE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x895ff000*/
442 #define SIPC_LTE_APCP_START_ADDR (PHYS_OFFSET_ADDR + LTE_CP_OFFSET_ADDR + LTE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x8ffff000*/
443 #define SIPC_PMIC_APCP_START_ADDR (PMIC_IRAM_ADDR+ PMIC_IRAM_SIZE+ - SIPC_APCP_RESET_ADDR_SIZE) /*0x50807400*/
444 #define CALIBRATION_FLAG_CP0 0x88AF0000
445 #define CALIBRATION_FLAG_CP1 0x8b770000
447 #define CONFIG_RAM_CONSOLE
449 #ifdef CONFIG_RAM_CONSOLE
450 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
451 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
455 #define CONFIG_CMD_SOUND 0
456 #define CONFIG_CMD_FOR_HTC 0
457 #define CONFIG_SOUND_CODEC_SPRD_V3 0
458 #define CONFIG_SOUND_DAI_VBC_R2P0 0
459 /* #define CONFIG_SPRD_AUDIO_DEBUG */
461 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
463 #define CONFIG_PBINT_7S_RESET_V1
465 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
467 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
468 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
469 #define CONFIG_7S_RST_2KEY_MODE 0 //0:1Key--Normal mode; 1:2KEY
470 #define CONFIG_7S_RST_THRESHOLD 7 //7S, hold key down for this time to trigger
472 #endif /* __CONFIG_H */