2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #define DT_PLATFROM_ID 8830
25 #define DT_HARDWARE_ID 1
26 #define DT_SOC_VER 0x20000
28 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
29 #define CONFIG_FDL2_PRINT 0
30 #define BOOT_NATIVE_LINUX 1
31 #define BOOT_NATIVE_LINUX_MODEM 1
32 #define CONFIG_SILENT_CONSOLE
33 #define CONFIG_GPIOLIB 1
36 #define CONFIG_SDRAMDISK
38 #define U_BOOT_SPRD_VER 1
39 /*#define SPRD_EVM_TAG_ON 1*/
40 #ifdef SPRD_EVM_TAG_ON
41 #define SPRD_EVM_ADDR_START 0x00026000
42 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
44 #define CONFIG_L2_OFF 1
48 #define CONFIG_YAFFS2 1
50 #define BOOT_PART "boot"
51 //#define BOOT_PART "kernel"
52 #define RECOVERY_PART "recovery"
54 * SPREADTRUM BIGPHONE board - SoC Configuration
56 #define CONFIG_AUTODLOADER
57 #define CONFIG_SP9630EA_4MOD
59 #define CONFIG_ADIE_SC2723
61 #define CONFIG_SPL_32K
63 //#define CONFIG_SUPPORT_TDLTE
64 #define TDDSP_ADR 0x88020000
65 #define CONFIG_SUPPORT_WLTE
66 //#define CONFIG_SUPPORT_GSM
68 #define LTE_GDSP_LOAD_OFFSET 0x20000
70 #define LTE_FIXNV_SIZE 0x00040000 //128k==>256k
71 #define LTE_RUNNV_SIZE 0x00060000 // 256K==>384K
72 #define LTE_FIXNV_ADDR 0x8b7d0000 //0x8a310000
73 #define LTE_RUNNV_ADDR 0x8b810000 //0x8a330000
74 #define LTE_MODEM_SIZE 0x009b0000 //0x8f0000
75 #define LTE_MODEM_ADDR 0x8ae00000
76 #define LTE_LDSP_SIZE 0x00b00000
77 #define LTE_LDSP_ADDR 0x89900000
78 #define LTE_GDSP_SIZE 0x002E0000
79 #define LTE_GDSP_ADDR (0x89600000 + LTE_GDSP_LOAD_OFFSET)
81 #define WL_WARM_SIZE 0x280000
82 #define WL_WARM_ADDR 0X8dc00000
84 #define GSM_FIXNV_SIZE 0x20000
85 #define GSM_FIXNV_ADDR 0x88a90000
86 #define GSM_RUNNV_SIZE 0x40000
87 #define GSM_RUNNV_ADDR 0x88ab0000
88 #define GSM_MODEM_ADDR 0X88400000 //equal to WL_DSDA_WARM_ADDR
89 #define GSM_MODEM_SIZE 0x670000 //equal to WL_DSDA_WARM_SIZE
90 #define GSM_DSP_ADDR 0x88000000
91 #define GSM_DSP_SIZE 0x400000
92 #define FIXNV_SIZE LTE_FIXNV_SIZE
94 #define CONFIG_DFS_ENABLE
95 #define DFS_ADDR 0x50800000
96 #define DFS_SIZE 32768 //32K
98 //#define CONFIG_CP0_ARM0_BOOT
99 #define CONFIG_PMIC_ARM7_BOOT
100 #define CONFIG_CP1_BOOT
101 #define CHIP_ENDIAN_LITTLE
102 #define _LITTLE_ENDIAN 1
104 #define CONFIG_RAM512M
106 #define CONFIG_EMMC_BOOT
107 #define CONFIG_ARCH_SCX35L
109 #ifdef CONFIG_EMMC_BOOT
110 #define EMMC_SECTOR_SIZE 512
112 #define CONFIG_FS_EXT4
113 #define CONFIG_EXT4_WRITE
114 #define CONFIG_CMD_EXT4
115 #define CONFIG_CMD_EXT4_WRITE
117 //#define CONFIG_TIGER_MMC
118 #define CONFIG_UEFI_PARTITION
119 #define CONFIG_EXT4_SPARSE_DOWNLOAD
120 //#define CONFIG_EMMC_SPL
121 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
127 #define CONFIG_CMD_MMC
128 #ifdef CONFIG_CMD_MMC
129 #define CONFIG_CMD_FAT 1
130 #define CONFIG_FAT_WRITE 1
132 #define CONFIG_GENERIC_MMC 1
133 #define CONFIG_SDHCI 1
134 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
135 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
136 #define CONFIG_MMC_SDMA 1
137 #define CONFIG_MV_SDHCI 1
138 #define CONFIG_DOS_PARTITION 1
139 #define CONFIG_EFI_PARTITION 1
140 #define CONFIG_SYS_MMC_NUM 1
143 #define BB_DRAM_TYPE_256MB_32BIT
145 #define CONFIG_SYS_HZ 1000
146 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
148 #define CP0_ZERO_MAP_ADR 0x50000000
149 #define CP0_ARM0_EXEC_ADR 0x88400000
151 #define CP1_ZERO_MAP_ADR 0x50001000
152 #define CP1_EXEC_ADR 0x8ae00000
154 #ifdef CONFIG_SYS_HUSH_PARSER
155 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
158 #define PRODUCTINFO_SIZE (16 * 1024)
159 #define MODEM_SIZE (0x800000)
160 #define DSP_SIZE (0x2E0000)
161 #define VMJALUNA_SIZE (0x64000) /* 400K */
162 #define RUNTIMENV_SIZE (3*128 * 1024)
163 #define CONFIG_SPL_LOAD_LEN (0x6000)
166 /*#define CMDLINE_NEED_CONV */
168 #define WATCHDOG_LOAD_VALUE 0x4000
169 #define CONFIG_SYS_STACK_SIZE 0x400
170 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
172 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
174 /* NAND BOOT is the only boot method */
175 #define CONFIG_NAND_U_BOOT
176 #define DYNAMIC_CRC_TABLE
177 /* Start copying real U-boot from the second page */
178 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
179 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
180 #define RAM_TYPPE_IS_SDRAM 0
181 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
183 /* IRAM store ddr info */
184 #define CONFIG_NR_DRAM_BANKS_ADDR_IN_IRAM 0x1C00
186 /* Load U-Boot to this address */
187 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
188 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
189 #define CONFIG_SYS_SDRAM_BASE 0x80000000
190 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
192 #ifdef CONFIG_NAND_SPL
193 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
196 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
197 #define CONFIG_SYS_INIT_SP_ADDR \
198 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SKIP_LOWLEVEL_INIT
203 #define CONFIG_HW_WATCHDOG
204 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
205 //#define CONFIG_DISPLAY_CPUINFO
207 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
208 #define CONFIG_SETUP_MEMORY_TAGS 1
209 #define CONFIG_INITRD_TAG 1
215 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
217 * Board has 2 32MB banks of DRAM but there is a bug when using
218 * both so only the first is configured
220 #define CONFIG_NR_DRAM_BANKS 1
222 #define PHYS_SDRAM_1 0x80000000
223 #define PHYS_SDRAM_1_SIZE 0x10000000
224 #if (CONFIG_NR_DRAM_BANKS == 2)
225 #define PHYS_SDRAM_2 0x90000000
226 #define PHYS_SDRAM_2_SIZE 0x10000000
229 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
230 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
231 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
236 #define CONFIG_SPRD_UART 1
237 #define CONFIG_SYS_SC8800X_UART1 1
238 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
239 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
240 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
241 #define CONFIG_SPRD_SPI
242 #define CONFIG_SPRD_I2C
243 #define CONFIG_SC9630_I2C
245 * Flash & Environment
247 /* No NOR flash present */
248 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
249 #define CONFIG_SYS_NO_FLASH 1
250 #define CONFIG_ENV_IS_NOWHERE
251 #define CONFIG_ENV_SIZE (128 * 1024)
253 #define CONFIG_ENV_IS_IN_NAND
254 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
255 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
260 //---these three macro below,only one can be open
265 //#define CONFIG_DDR_AUTO_DETECT
266 #define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
267 //#define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
268 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
269 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
270 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
271 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
273 #define DDR3_DLL_ON TRUE
275 #define DDR_APB_CLK 128
276 #define DDR_DFS_SUPPORT
277 #define DDR_DFS_VAL_BASE 0X1c00
279 //#define DDR_SCAN_SUPPORT
280 #define MEM_IO_DS LPDDR2_DS_40R
282 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
283 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
284 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
287 #define CONFIG_NAND_SC9630
288 #define CONFIG_SPRD_NAND_REGS_BASE (0x21100000)
289 #define CONFIG_SYS_MAX_NAND_DEVICE 1
290 #define CONFIG_SYS_NAND_BASE (0x21100000)
291 //#define CONFIG_JFFS2_NAND
292 //#define CONFIG_SPRD_NAND_HWECC
293 #define CONFIG_SYS_NAND_HW_ECC
294 #define CONFIG_SYS_NAND_LARGEPAGE
295 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
297 #define CONFIG_SYS_64BIT_VSPRINTF
299 #define CONFIG_CMD_MTDPARTS
300 #define CONFIG_MTD_PARTITIONS
301 #define CONFIG_MTD_DEVICE
302 #define CONFIG_CMD_UBI
303 #define CONFIG_RBTREE
305 /* U-Boot general configuration */
306 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
307 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
308 /* Print buffer sz */
309 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
310 sizeof(CONFIG_SYS_PROMPT) + 16)
311 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
312 /* Boot Argument Buffer Size */
313 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
314 #define CONFIG_CMDLINE_EDITING
315 #define CONFIG_SYS_LONGHELP
317 /* support OS choose */
318 #undef CONFIG_BOOTM_NETBSD
319 #undef CONFIG_BOOTM_RTEMS
321 /* U-Boot commands */
322 #include <config_cmd_default.h>
323 #define CONFIG_CMD_NAND
324 #undef CONFIG_CMD_FPGA
325 #undef CONFIG_CMD_LOADS
326 #undef CONFIG_CMD_NET
327 #undef CONFIG_CMD_NFS
328 #undef CONFIG_CMD_SETGETDCR
330 #define CONFIG_ENV_OVERWRITE
332 #ifdef SPRD_EVM_TAG_ON
333 #define CONFIG_BOOTDELAY 0
335 #define CONFIG_BOOTDELAY 0
336 #define CONFIG_ZERO_BOOTDELAY_CHECK
339 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
340 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
342 #define xstr(s) str(s)
345 #define MTDIDS_DEFAULT "nand0=sprd-nand"
346 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
347 #define CONFIG_BOOTARGS "mem=512M loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
349 #define COPY_LINUX_KERNEL_SIZE (0x600000)
350 #define LINUX_INITRD_NAME "modem"
352 #define CONFIG_BOOTCOMMAND "cboot normal"
353 #define CONFIG_EXTRA_ENV_SETTINGS ""
355 #ifdef CONFIG_CMD_NET
356 #define CONFIG_IPADDR 192.168.10.2
357 #define CONFIG_SERVERIP 192.168.10.5
358 #define CONFIG_NETMASK 255.255.255.0
359 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
360 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
363 #define CONFIG_NET_MULTI
364 #define CONFIG_CMD_DNS
365 #define CONFIG_CMD_NFS
366 #define CONFIG_CMD_RARP
367 #define CONFIG_CMD_PING
368 /*#define CONFIG_CMD_SNTP */
371 #define CONFIG_USB_CORE_IP_293A
372 #define CONFIG_USB_GADGET_SC8800G
373 #define CONFIG_USB_DWC
374 #define CONFIG_USB_GADGET_DUALSPEED
375 //#define CONFIG_USB_ETHER
376 #define CONFIG_CMD_FASTBOOT
377 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
378 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
379 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
380 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
381 #define CONFIG_MODEM_CALIBERATE
385 #define CONFIG_DSIH_VERSION_1P21A
386 #define CONFIG_SPLASH_SCREEN
387 #define LCD_BPP LCD_COLOR16
388 #define CONFIG_LCD_FWVGA
389 //#define CONFIG_LCD_WVGA 1
390 //#define CONFIG_LCD_HVGA 1
391 //#define CONFIG_LCD_QVGA 1
392 //#define CONFIG_LCD_QHD 1
393 //#define CONFIG_LCD_720P 1
394 //#define CONFIG_LCD_INFO
395 //#define LCD_TEST_PATTERN
396 //#define CONFIG_LCD_LOGO
397 //#define CONFIG_FB_LCD_S6D0139
398 //#define CONFIG_FB_LCD_RM68180_MIPI
399 //#define CONFIG_FB_LCD_NT35516_MIPI
400 #define CONFIG_FB_LCD_ILI9806E_2_MIPI
401 #define CONFIG_FB_LCD_OTM8019A_MIPI
402 #define CONFIG_SYS_WHITE_ON_BLACK
403 #ifdef LCD_TEST_PATTERN
404 #define CONSOLE_COLOR_RED 0xf800
405 #define CONSOLE_COLOR_GREEN 0x07e0
406 #define CONSOLE_COLOR_YELLOW 0x07e0
407 #define CONSOLE_COLOR_BLUE 0x001f
408 #define CONSOLE_COLOR_MAGENTA 0x001f
409 #define CONSOLE_COLOR_CYAN 0x001f
413 #define CONFIG_SPRD_SYSDUMP
414 #include <asm/sizes.h>
415 #if !defined(CONFIG_DDR_AUTO_DETECT)
416 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
420 #define CALIBRATE_ENUM_MS 3000
421 #define CALIBRATE_IO_MS 2000
423 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
424 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
425 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
427 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
428 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
430 #define PHYS_OFFSET_ADDR 0x80000000
431 //#define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
432 //#define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
433 //#define WCDMA_CP_OFFSET_ADDR 0x10000000 /*256M*/
434 //#define WCDMA_CP_SDRAM_SIZE 0x4000000 /*64M*/
435 #define GGE_CP_OFFSET_ADDR 0x08000000 /*128M*/
436 #define GGE_CP_SDRAM_SIZE 0x01600000 /*22M*/
437 #define LTE_CP_OFFSET_ADDR 0x09600000 /*150M*/
438 #define LTE_CP_SDRAM_SIZE 0x04300000 /*67M*/
439 #define PMIC_IRAM_ADDR 0x50800000 /*pmic arm7 iram address remap at AP side*/
440 #define PMIC_IRAM_SIZE 0x8000 /*32K*/
441 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
442 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
443 #define CALIBRATION_CMDLINE_SIZE 0x400 /*1K*/
444 //#define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
445 //#define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x93FFF000*/
446 #define SIPC_GGE_APCP_START_ADDR (PHYS_OFFSET_ADDR + GGE_CP_OFFSET_ADDR + GGE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x895ff000*/
447 #define SIPC_LTE_APCP_START_ADDR (PHYS_OFFSET_ADDR + LTE_CP_OFFSET_ADDR + LTE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x8ffff000*/
448 #define SIPC_PMIC_APCP_START_ADDR (PMIC_IRAM_ADDR+ PMIC_IRAM_SIZE+ - SIPC_APCP_RESET_ADDR_SIZE) /*0x50807400*/
449 #define CALIBRATION_FLAG_CP0 0x88AF0000
450 #define CALIBRATION_FLAG_CP1 0x8b870000
452 #define CONFIG_RAM_CONSOLE
454 #ifdef CONFIG_RAM_CONSOLE
455 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
456 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
460 #define CONFIG_CMD_SOUND 0
461 #define CONFIG_CMD_FOR_HTC 0
462 #define CONFIG_SOUND_CODEC_SPRD_V3 0
463 #define CONFIG_SOUND_DAI_VBC_R2P0 0
464 /* #define CONFIG_SPRD_AUDIO_DEBUG */
466 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
468 #define CONFIG_PBINT_7S_RESET_V1
470 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
472 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
473 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
474 #define CONFIG_7S_RST_2KEY_MODE 0 //0:1Key--Normal mode; 1:2KEY
475 #define CONFIG_7S_RST_THRESHOLD 7 //7S, hold key down for this time to trigger
477 #endif /* __CONFIG_H */