2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 //#define CONFIG_SECURE_BOOT
25 //#define CONFIG_ROM_VERIFY_SPL
26 #define PRIMPUKPATH "/dev/block/mmcblk0boot0"
27 #define PRIMPUKSTART 512
28 #define PRIMPUKLEN 260
30 #define DT_PLATFROM_ID 8830
31 #define DT_HARDWARE_ID 1
32 #define DT_SOC_VER 0x20000
34 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
35 #define CONFIG_FDL2_PRINT 0
36 #define BOOT_NATIVE_LINUX 1
37 #define BOOT_NATIVE_LINUX_MODEM 1
38 #define CONFIG_SILENT_CONSOLE
39 #define CONFIG_GPIOLIB 1
42 #define CONFIG_SDRAMDISK
44 #define U_BOOT_SPRD_VER 1
45 /*#define SPRD_EVM_TAG_ON 1*/
46 #ifdef SPRD_EVM_TAG_ON
47 #define SPRD_EVM_ADDR_START 0x00026000
48 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
50 #define CONFIG_L2_OFF 1
54 #define CONFIG_YAFFS2 1
56 #define BOOT_PART "boot"
57 //#define BOOT_PART "kernel"
58 #define RECOVERY_PART "recovery"
60 * SPREADTRUM BIGPHONE board - SoC Configuration
62 #define CONFIG_AUTODLOADER
63 #define CONFIG_SP9630EA
65 #define CONFIG_ADIE_SC2723
67 #define CONFIG_SPL_32K
69 #define CONFIG_SUPPORT_TDLTE
70 #define TDDSP_ADR 0x88020000
71 //#define CONFIG_SUPPORT_WLTE
72 //#define CONFIG_SUPPORT_GSM
74 #define LTE_GDSP_LOAD_OFFSET 0x20000
76 #define LTE_FIXNV_SIZE 0x00040000 //128k==>256k
77 #define LTE_RUNNV_SIZE 0x00060000 // 256K==>384K
78 #define LTE_FIXNV_ADDR 0x8b6d0000 //0x8a310000
79 #define LTE_RUNNV_ADDR 0x8b710000 //0x8a330000
80 #define LTE_MODEM_SIZE 0x008b0000 //0x8f0000
81 #define LTE_MODEM_ADDR 0x8ae00000
82 #define LTE_LDSP_SIZE 0x00b00000
83 #define LTE_LDSP_ADDR 0x89900000
84 #define LTE_GDSP_SIZE 0x002E0000
85 #define LTE_GDSP_ADDR (0x89600000 + LTE_GDSP_LOAD_OFFSET)
87 #define WL_WARM_SIZE 0x670000
88 #define WL_WARM_ADDR 0X88400000
90 #define GSM_FIXNV_SIZE 0x20000
91 #define GSM_FIXNV_ADDR 0x88a90000
92 #define GSM_RUNNV_SIZE 0x40000
93 #define GSM_RUNNV_ADDR 0x88ab0000
94 #define GSM_MODEM_ADDR 0X88400000 //equal to WL_DSDA_WARM_ADDR
95 #define GSM_MODEM_SIZE 0x670000 //equal to WL_DSDA_WARM_SIZE
96 #define GSM_DSP_ADDR 0x88000000
97 #define GSM_DSP_SIZE 0x400000
98 #define FIXNV_SIZE LTE_FIXNV_SIZE
100 #define CONFIG_DFS_ENABLE
101 #define DFS_ADDR 0x50800000
102 #define DFS_SIZE 32768 //32K
104 //#define CONFIG_CP0_ARM0_BOOT
105 #define CONFIG_PMIC_ARM7_BOOT
106 #define CONFIG_CP1_BOOT
107 #define CHIP_ENDIAN_LITTLE
108 #define _LITTLE_ENDIAN 1
110 #define CONFIG_RAM512M
112 #define CONFIG_EMMC_BOOT
113 #define CONFIG_ARCH_SCX35L
115 #ifdef CONFIG_EMMC_BOOT
116 #define EMMC_SECTOR_SIZE 512
118 #define CONFIG_FS_EXT4
119 #define CONFIG_EXT4_WRITE
120 #define CONFIG_CMD_EXT4
121 #define CONFIG_CMD_EXT4_WRITE
123 //#define CONFIG_TIGER_MMC
124 #define CONFIG_UEFI_PARTITION
125 #define CONFIG_EXT4_SPARSE_DOWNLOAD
126 //#define CONFIG_EMMC_SPL
127 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
133 #define CONFIG_CMD_MMC
134 #ifdef CONFIG_CMD_MMC
135 #define CONFIG_CMD_FAT 1
136 #define CONFIG_FAT_WRITE 1
138 #define CONFIG_GENERIC_MMC 1
139 #define CONFIG_SDHCI 1
140 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
141 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
142 #define CONFIG_MMC_SDMA 1
143 #define CONFIG_MV_SDHCI 1
144 #define CONFIG_DOS_PARTITION 1
145 #define CONFIG_EFI_PARTITION 1
146 #define CONFIG_SYS_MMC_NUM 1
149 #define BB_DRAM_TYPE_256MB_32BIT
151 #define CONFIG_SYS_HZ 1000
152 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
154 #define CP0_ZERO_MAP_ADR 0x50000000
155 #define CP0_ARM0_EXEC_ADR 0x88400000
157 #define CP1_ZERO_MAP_ADR 0x50001000
158 #define CP1_EXEC_ADR 0x8ae00000
160 #ifdef CONFIG_SYS_HUSH_PARSER
161 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
164 #define PRODUCTINFO_SIZE (16 * 1024)
165 #define MODEM_SIZE (0x800000)
166 #define DSP_SIZE (0x2E0000)
167 #define VMJALUNA_SIZE (0x64000) /* 400K */
168 #define RUNTIMENV_SIZE (3*128 * 1024)
170 #ifdef CONFIG_ROM_VERIFY_SPL
171 #define CONFIG_SPL_LOAD_LEN (0x8000) /* 32 KB */
172 #define CONFIG_BOOTINFO_LENGTH (0x200) /* 512 Bytes*/
173 #define PUBKEY_BSC_BLOCK_INDEX (CONFIG_SPL_LOAD_LEN - CONFIG_BOOTINFO_LENGTH * 2) / EMMC_SECTOR_SIZE
174 #define PUBKEY_VLR_BLOCK_INDEX 2
175 #define PUBKEY_READ_BLOCK_NUMS 1
176 #define CONFIG_SPL_HASH_LEN (0x400) /* 1KB */
178 #define CONFIG_SPL_LOAD_LEN (0x6000)
179 #define PUBKEY_BSC_BLOCK_INDEX 0
180 #define PUBKEY_VLR_BLOCK_INDEX 0
181 #define PUBKEY_READ_BLOCK_NUMS (SEC_HEADER_MAX_SIZE / EMMC_SECTOR_SIZE)
182 #define CONFIG_SPL_HASH_LEN (0xC00) /* 3KB */
187 /*#define CMDLINE_NEED_CONV */
189 #define WATCHDOG_LOAD_VALUE 0x4000
190 #define CONFIG_SYS_STACK_SIZE 0x400
191 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
193 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
195 /* NAND BOOT is the only boot method */
196 #define CONFIG_NAND_U_BOOT
197 #define DYNAMIC_CRC_TABLE
198 /* Start copying real U-boot from the second page */
199 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
200 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
201 #define RAM_TYPPE_IS_SDRAM 0
202 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
204 /* IRAM store ddr info */
205 #define CONFIG_NR_DRAM_BANKS_ADDR_IN_IRAM 0x1C00
207 /* Load U-Boot to this address */
208 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
209 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
210 #define CONFIG_SYS_SDRAM_BASE 0x80000000
211 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
213 #ifdef CONFIG_NAND_SPL
214 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
217 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
218 #define CONFIG_SYS_INIT_SP_ADDR \
219 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
221 #define CONFIG_SKIP_LOWLEVEL_INIT
224 #define CONFIG_HW_WATCHDOG
225 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
226 //#define CONFIG_DISPLAY_CPUINFO
228 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
229 #define CONFIG_SETUP_MEMORY_TAGS 1
230 #define CONFIG_INITRD_TAG 1
236 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
238 * Board has 2 32MB banks of DRAM but there is a bug when using
239 * both so only the first is configured
241 #define CONFIG_NR_DRAM_BANKS 1
243 #define PHYS_SDRAM_1 0x80000000
244 #define PHYS_SDRAM_1_SIZE 0x10000000
245 #if (CONFIG_NR_DRAM_BANKS == 2)
246 #define PHYS_SDRAM_2 0x90000000
247 #define PHYS_SDRAM_2_SIZE 0x10000000
250 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
251 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
252 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
257 #define CONFIG_SPRD_UART 1
258 #define CONFIG_SYS_SC8800X_UART1 1
259 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
260 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
261 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
262 #define CONFIG_SPRD_SPI
263 #define CONFIG_SPRD_I2C
264 #define CONFIG_SC9630_I2C
266 * Flash & Environment
268 /* No NOR flash present */
269 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
270 #define CONFIG_SYS_NO_FLASH 1
271 #define CONFIG_ENV_IS_NOWHERE
272 #define CONFIG_ENV_SIZE (128 * 1024)
274 #define CONFIG_ENV_IS_IN_NAND
275 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
276 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
281 //---these three macro below,only one can be open
286 //#define CONFIG_DDR_AUTO_DETECT
287 #define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
288 //#define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
289 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
290 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
291 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
292 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
294 #define DDR3_DLL_ON TRUE
296 #define DDR_APB_CLK 128
297 #define DDR_DFS_SUPPORT
298 #define DDR_DFS_VAL_BASE 0X1c00
300 //#define DDR_SCAN_SUPPORT
301 #define MEM_IO_DS LPDDR2_DS_40R
303 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
304 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
305 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
308 #define CONFIG_NAND_SC9630
309 #define CONFIG_SPRD_NAND_REGS_BASE (0x21100000)
310 #define CONFIG_SYS_MAX_NAND_DEVICE 1
311 #define CONFIG_SYS_NAND_BASE (0x21100000)
312 //#define CONFIG_JFFS2_NAND
313 //#define CONFIG_SPRD_NAND_HWECC
314 #define CONFIG_SYS_NAND_HW_ECC
315 #define CONFIG_SYS_NAND_LARGEPAGE
316 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
318 #define CONFIG_SYS_64BIT_VSPRINTF
320 #define CONFIG_CMD_MTDPARTS
321 #define CONFIG_MTD_PARTITIONS
322 #define CONFIG_MTD_DEVICE
323 #define CONFIG_CMD_UBI
324 #define CONFIG_RBTREE
326 /* U-Boot general configuration */
327 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
328 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
329 /* Print buffer sz */
330 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
331 sizeof(CONFIG_SYS_PROMPT) + 16)
332 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
333 /* Boot Argument Buffer Size */
334 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
335 #define CONFIG_CMDLINE_EDITING
336 #define CONFIG_SYS_LONGHELP
338 /* support OS choose */
339 #undef CONFIG_BOOTM_NETBSD
340 #undef CONFIG_BOOTM_RTEMS
342 /* U-Boot commands */
343 #include <config_cmd_default.h>
344 #define CONFIG_CMD_NAND
345 #undef CONFIG_CMD_FPGA
346 #undef CONFIG_CMD_LOADS
347 #undef CONFIG_CMD_NET
348 #undef CONFIG_CMD_NFS
349 #undef CONFIG_CMD_SETGETDCR
351 #define CONFIG_ENV_OVERWRITE
353 #ifdef SPRD_EVM_TAG_ON
354 #define CONFIG_BOOTDELAY 0
356 #define CONFIG_BOOTDELAY 0
357 #define CONFIG_ZERO_BOOTDELAY_CHECK
360 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
361 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
363 #define xstr(s) str(s)
366 #define MTDIDS_DEFAULT "nand0=sprd-nand"
367 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
368 #define CONFIG_BOOTARGS "mem=512M loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
370 #define COPY_LINUX_KERNEL_SIZE (0x600000)
371 #define LINUX_INITRD_NAME "modem"
373 #define CONFIG_BOOTCOMMAND "cboot normal"
374 #define CONFIG_EXTRA_ENV_SETTINGS ""
376 #ifdef CONFIG_CMD_NET
377 #define CONFIG_IPADDR 192.168.10.2
378 #define CONFIG_SERVERIP 192.168.10.5
379 #define CONFIG_NETMASK 255.255.255.0
380 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
381 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
384 #define CONFIG_NET_MULTI
385 #define CONFIG_CMD_DNS
386 #define CONFIG_CMD_NFS
387 #define CONFIG_CMD_RARP
388 #define CONFIG_CMD_PING
389 /*#define CONFIG_CMD_SNTP */
392 #define CONFIG_USB_CORE_IP_293A
393 #define CONFIG_USB_GADGET_SC8800G
394 #define CONFIG_USB_DWC
395 #define CONFIG_USB_GADGET_DUALSPEED
396 //#define CONFIG_USB_ETHER
397 #define CONFIG_CMD_FASTBOOT
398 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
399 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
400 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
401 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
402 #define CONFIG_MODEM_CALIBERATE
406 #define CONFIG_DSIH_VERSION_1P21A
407 #define CONFIG_SPLASH_SCREEN
408 #define LCD_BPP LCD_COLOR16
409 #define CONFIG_LCD_WVGA 1
410 //#define CONFIG_LCD_HVGA 1
411 //#define CONFIG_LCD_QVGA 1
412 //#define CONFIG_LCD_QHD 1
413 //#define CONFIG_LCD_720P 1
414 //#define CONFIG_LCD_INFO
415 //#define LCD_TEST_PATTERN
416 //#define CONFIG_LCD_LOGO
417 //#define CONFIG_FB_LCD_S6D0139
418 #define CONFIG_FB_LCD_RM68180_MIPI
419 #define CONFIG_FB_LCD_NT35516_MIPI
420 #define CONFIG_FB_LCD_ILI9806E_MIPI
421 #define CONFIG_SYS_WHITE_ON_BLACK
422 #ifdef LCD_TEST_PATTERN
423 #define CONSOLE_COLOR_RED 0xf800
424 #define CONSOLE_COLOR_GREEN 0x07e0
425 #define CONSOLE_COLOR_YELLOW 0x07e0
426 #define CONSOLE_COLOR_BLUE 0x001f
427 #define CONSOLE_COLOR_MAGENTA 0x001f
428 #define CONSOLE_COLOR_CYAN 0x001f
432 #define CONFIG_SPRD_SYSDUMP
433 #include <asm/sizes.h>
434 #if !defined(CONFIG_DDR_AUTO_DETECT)
435 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
438 #define CALIBRATE_ENUM_MS 3000
439 #define CALIBRATE_IO_MS 2000
441 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
442 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
443 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
445 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
446 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
448 #define PHYS_OFFSET_ADDR 0x80000000
449 //#define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
450 //#define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
451 //#define WCDMA_CP_OFFSET_ADDR 0x10000000 /*256M*/
452 //#define WCDMA_CP_SDRAM_SIZE 0x4000000 /*64M*/
453 #define GGE_CP_OFFSET_ADDR 0x08000000 /*128M*/
454 #define GGE_CP_SDRAM_SIZE 0x01600000 /*22M*/
455 #define LTE_CP_OFFSET_ADDR 0x09600000 /*150M*/
456 #define LTE_CP_SDRAM_SIZE 0x04000000 /*64M*/
457 #define PMIC_IRAM_ADDR 0x50800000 /*pmic arm7 iram address remap at AP side*/
458 #define PMIC_IRAM_SIZE 0x8000 /*32K*/
459 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
460 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
461 #define CALIBRATION_CMDLINE_SIZE 0x400 /*1K*/
462 //#define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
463 //#define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x93FFF000*/
464 #define SIPC_GGE_APCP_START_ADDR (PHYS_OFFSET_ADDR + GGE_CP_OFFSET_ADDR + GGE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x895ff000*/
465 #define SIPC_LTE_APCP_START_ADDR (PHYS_OFFSET_ADDR + LTE_CP_OFFSET_ADDR + LTE_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x8ffff000*/
466 #define SIPC_PMIC_APCP_START_ADDR (PMIC_IRAM_ADDR+ PMIC_IRAM_SIZE+ - SIPC_APCP_RESET_ADDR_SIZE) /*0x50807400*/
467 #define CALIBRATION_FLAG_CP0 0x88AF0000
468 #define CALIBRATION_FLAG_CP1 0x8b770000
470 #define CONFIG_RAM_CONSOLE
472 #ifdef CONFIG_RAM_CONSOLE
473 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
474 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
478 #define CONFIG_CMD_SOUND 0
479 #define CONFIG_CMD_FOR_HTC 0
480 #define CONFIG_SOUND_CODEC_SPRD_V3 0
481 #define CONFIG_SOUND_DAI_VBC_R2P0 0
482 /* #define CONFIG_SPRD_AUDIO_DEBUG */
484 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
486 #define CONFIG_PBINT_7S_RESET_V1
488 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
490 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
491 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
492 #define CONFIG_7S_RST_2KEY_MODE 0 //0:1Key--Normal mode; 1:2KEY
493 #define CONFIG_7S_RST_THRESHOLD 7 //7S, hold key down for this time to trigger
496 #endif /* __CONFIG_H */