2 * (C) Copyright 2009 DENX Software Engineering
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3 * Author: John Rigby <jrigby@gmail.com>
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5 * This program is free software; you can redistribute it and/or
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6 * modify it under the terms of the GNU General Public License as
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7 * published by the Free Software Foundation; either version 2 of
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8 * the License, or (at your option) any later version.
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10 * This program is distributed in the hope that it will be useful,
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 * GNU General Public License for more details.
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15 * You should have received a copy of the GNU General Public License
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16 * along with this program; if not, write to the Free Software
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17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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24 //#define CONFIG_OF_LIBFDT
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25 //#ifdef CONFIG_OF_LIBFDT
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26 //MACH_TYPE_SC8830=2014
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28 #define DT_PLATFROM_ID 8830
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29 #define DT_HARDWARE_ID 1
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30 #define DT_SOC_VER 0x20000
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32 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
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33 #define CONFIG_FDL2_PRINT 0
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34 #define BOOT_NATIVE_LINUX 1
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35 #define BOOT_NATIVE_LINUX_MODEM 1
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36 //#define CALIBRATION_FLAG 0x897FFC00
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37 //#define CALIBRATION_FLAG_WCDMA 0x93FFEC00
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38 #define CONFIG_SILENT_CONSOLE
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39 #define CONFIG_GPIOLIB 1
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40 //#define NAND_DEBUG
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42 #define CONFIG_SDRAMDISK
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43 #define U_BOOT_SPRD_VER 1
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44 /*#define SPRD_EVM_TAG_ON 1*/
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45 #ifdef SPRD_EVM_TAG_ON
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46 #define SPRD_EVM_ADDR_START 0x00026000
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47 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
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49 #define CONFIG_L2_OFF 1
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51 #define BOOT_DEBUG 1
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53 #define CONFIG_YAFFS2 1
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55 #define BOOT_PART "boot"
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56 //#define BOOT_PART "kernel"
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57 #define RECOVERY_PART "recovery"
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59 * SPREADTRUM BIGPHONE board - SoC Configuration
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61 #define CONFIG_SP8830
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62 #define CONFIG_SC8830
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63 #define CONFIG_SP8830EC
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64 #define CONFIG_SP8830WCN
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67 #define CONFIG_SUPPORT_TD
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68 #define TDDSP_ADR 0x88020000
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69 #define TDFIXNV_ADR 0x89060000
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70 #define TDRUNTIMENV_ADR 0x890a0000
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71 #define TDMODEM_ADR 0x88300000
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72 #define CONFIG_SUPPORT_WIFI
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73 #define WCNMODEM_ADR 0x94060000
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74 #define WCNFIXNV_ADR 0x94000000
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75 #define WCNRUNTIMENV_ADR 0x94020000
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76 #define CP0_CODE_COPY_ADR 0x50000000
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77 #define CP1_CODE_COPY_ADR 0x50001800
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78 #define CP2_CODE_COPY_ADR 0x50003000
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79 #define CP_SOFT_RST_ADR 0x402B00A8
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80 #define PD_CP0_SYS_CFG_ADR 0x402B003C
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81 #define PD_CP1_SYS_CFG_ADR 0x402B0050
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82 #define PD_CP2_SYS_CFG_ADR 0x402B0060
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83 #define PD_CP2_ARM9_CFG_ADR 0x402B0054
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84 #define PWR_STATUS1_DBG_ADR 0x402B00B8
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85 #define PWR_STATUS2_DBG_ADR 0x402B00BC
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86 #define PWR_STATUS3_DBG_ADR 0x402B00C0
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88 #define CONFIG_AUTODLOADER
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89 #define CONFIG_SIMLOCK_ENABLE
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91 #define CHIP_ENDIAN_LITTLE
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92 #define _LITTLE_ENDIAN 1
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94 #define CONFIG_RAM512M
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96 #define CONFIG_EMMC_BOOT
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98 #ifdef CONFIG_EMMC_BOOT
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99 #define EMMC_SECTOR_SIZE 512
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102 #define CONFIG_FS_EXT4
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103 #define CONFIG_EXT4_WRITE
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104 #define CONFIG_CMD_EXT4
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105 #define CONFIG_CMD_EXT4_WRITE
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107 //#define CONFIG_TIGER_MMC
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108 #define CONFIG_UEFI_PARTITION
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109 #define CONFIG_EFI_PARTITION
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110 #define CONFIG_EXT4_SPARSE_DOWNLOAD
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111 //#define CONFIG_EMMC_SPL
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112 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
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119 #define CONFIG_CMD_MMC
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120 #ifdef CONFIG_CMD_MMC
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121 #define CONFIG_CMD_FAT 1
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122 #define CONFIG_FAT_WRITE 1
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123 #define CONFIG_MMC 1
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124 #define CONFIG_GENERIC_MMC 1
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125 #define CONFIG_SDHCI 1
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126 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
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127 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
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128 #define CONFIG_MMC_SDMA 1
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129 #define CONFIG_MV_SDHCI 1
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130 #define CONFIG_DOS_PARTITION 1
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131 #define CONFIG_EFI_PARTITION 1
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132 #define CONFIG_SYS_MMC_NUM 1
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133 #define CONFIG_SYS_MMC_BASE {0x20600000}
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134 #define CONFIG_SYS_SD_BASE 0x20300000
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137 #define BB_DRAM_TYPE_256MB_32BIT
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139 #define CONFIG_SYS_HZ 1000
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140 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
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142 //#define CONFIG_SYS_HUSH_PARSER
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144 #ifdef CONFIG_SYS_HUSH_PARSER
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145 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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148 #define FIXNV_SIZE (2*128 * 1024)
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149 #define TDMODEM_SIZE (0x600000)
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150 #define TDDSP_SIZE (0x2E0000)
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151 #define WCNMODEM_SIZE (0x800000)
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152 #define VMJALUNA_SIZE (0x64000) /* 400K */
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153 #define RUNTIMENV_SIZE (3*128 * 1024)
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154 #define CONFIG_SPL_LOAD_LEN (0x6000)
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157 /*#define CMDLINE_NEED_CONV */
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159 #define WATCHDOG_LOAD_VALUE 0x4000
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160 #define CONFIG_SYS_STACK_SIZE 0x400
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161 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
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163 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
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165 /* NAND BOOT is the only boot method */
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166 #define CONFIG_NAND_U_BOOT
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167 #define DYNAMIC_CRC_TABLE
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168 /* Start copying real U-boot from the second page */
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169 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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170 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
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171 #define RAM_TYPPE_IS_SDRAM 0
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172 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
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174 /* Load U-Boot to this address */
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175 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
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176 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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177 #define CONFIG_SYS_SDRAM_BASE 0x80000000
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178 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
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180 #ifdef CONFIG_NAND_SPL
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181 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
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184 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
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185 #define CONFIG_SYS_INIT_SP_ADDR \
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186 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
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188 #define CONFIG_SKIP_LOWLEVEL_INIT
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191 #define CONFIG_HW_WATCHDOG
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192 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
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193 //#define CONFIG_DISPLAY_CPUINFO
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195 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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196 #define CONFIG_SETUP_MEMORY_TAGS 1
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197 #define CONFIG_INITRD_TAG 1
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203 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
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205 * Board has 2 32MB banks of DRAM but there is a bug when using
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206 * both so only the first is configured
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208 #define CONFIG_NR_DRAM_BANKS 1
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210 #define PHYS_SDRAM_1 0x80000000
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211 #define PHYS_SDRAM_1_SIZE 0x10000000
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212 #if (CONFIG_NR_DRAM_BANKS == 2)
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213 #define PHYS_SDRAM_2 0x90000000
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214 #define PHYS_SDRAM_2_SIZE 0x10000000
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216 /* 8MB DRAM test */
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217 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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218 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
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219 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
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224 #define CONFIG_SPRD_UART 1
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225 #define CONFIG_SYS_SC8800X_UART1 1
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226 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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227 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
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228 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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229 #define CONFIG_SPRD_SPI
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230 #define CONFIG_SPRD_I2C
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231 #define CONFIG_SC8830_I2C
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233 * Flash & Environment
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235 /* No NOR flash present */
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236 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
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237 #define CONFIG_SYS_NO_FLASH 1
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238 #define CONFIG_ENV_IS_NOWHERE
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239 #define CONFIG_ENV_SIZE (128 * 1024)
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241 #define CONFIG_ENV_IS_IN_NAND
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242 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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243 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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247 #define DDR_CLK 464
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248 //---these three macro below,only one can be open
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249 //#define DDR_LPDDR1
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253 //#define DDR_AUTO_DETECT
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254 #define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
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255 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
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256 //#define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
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257 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
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258 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
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259 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
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261 #define DDR3_DLL_ON TRUE
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262 //#define DLL_BYPASS
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263 #define DDR_APB_CLK 128
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264 #define DDR_DFS_SUPPORT
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265 #define DDR_DFS_VAL_BASE 0X1c00
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267 //#define DDR_SCAN_SUPPORT
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268 #define MEM_IO_DS LPDDR2_DS_40R
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270 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
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271 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
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272 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
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277 #define CONFIG_NAND_SC8830
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278 #define CONFIG_SPRD_NAND_REGS_BASE (0x21100000)
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279 #define CONFIG_SYS_MAX_NAND_DEVICE 1
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280 #define CONFIG_SYS_NAND_BASE (0x21100000)
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281 //#define CONFIG_JFFS2_NAND
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282 //#define CONFIG_SPRD_NAND_HWECC
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283 #define CONFIG_SYS_NAND_HW_ECC
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284 #define CONFIG_SYS_NAND_LARGEPAGE
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285 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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287 #define CONFIG_SYS_64BIT_VSPRINTF
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289 #define CONFIG_CMD_MTDPARTS
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290 #define CONFIG_MTD_PARTITIONS
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291 #define CONFIG_MTD_DEVICE
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292 #define CONFIG_CMD_UBI
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293 #define CONFIG_RBTREE
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295 /* U-Boot general configuration */
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296 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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297 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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298 /* Print buffer sz */
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299 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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300 sizeof(CONFIG_SYS_PROMPT) + 16)
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301 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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302 /* Boot Argument Buffer Size */
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303 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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304 #define CONFIG_CMDLINE_EDITING
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305 #define CONFIG_SYS_LONGHELP
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307 /* support OS choose */
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308 #undef CONFIG_BOOTM_NETBSD
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309 #undef CONFIG_BOOTM_RTEMS
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311 /* U-Boot commands */
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312 #include <config_cmd_default.h>
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313 #define CONFIG_CMD_NAND
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314 #undef CONFIG_CMD_FPGA
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315 #undef CONFIG_CMD_LOADS
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316 #undef CONFIG_CMD_NET
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317 #undef CONFIG_CMD_NFS
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318 #undef CONFIG_CMD_SETGETDCR
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320 #define CONFIG_ENV_OVERWRITE
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322 #ifdef SPRD_EVM_TAG_ON
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323 #define CONFIG_BOOTDELAY 0
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325 #define CONFIG_BOOTDELAY 0
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326 #define CONFIG_ZERO_BOOTDELAY_CHECK
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329 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
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330 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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332 #define xstr(s) str(s)
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335 #ifdef CONFIG_RAM512M
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336 #define MEM_INIT_PARA "mem=512M"
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337 #elif defined(CONFIG_RAM256M)
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338 #define MEM_INIT_PARA "mem=256M"
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339 //#elif defined(CONFIG_RAMxxxM)
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340 ////#define MEM_INIT_PARA "mem=xxxM" //xxx maybe 1024 etc
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342 #error "CONFIG_RAMxxxM macro must be defined"
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344 #define MTDIDS_DEFAULT "nand0=sprd-nand"
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345 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
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346 #define CONFIG_BOOTARGS MEM_INIT_PARA" loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
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348 #define COPY_LINUX_KERNEL_SIZE (0x600000)
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349 #define LINUX_INITRD_NAME "modem"
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351 #define CONFIG_BOOTCOMMAND "cboot normal"
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352 #define CONFIG_EXTRA_ENV_SETTINGS ""
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354 #ifdef CONFIG_CMD_NET
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355 #define CONFIG_IPADDR 192.168.10.2
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356 #define CONFIG_SERVERIP 192.168.10.5
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357 #define CONFIG_NETMASK 255.255.255.0
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358 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
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359 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
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362 #define CONFIG_NET_MULTI
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363 #define CONFIG_CMD_DNS
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364 #define CONFIG_CMD_NFS
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365 #define CONFIG_CMD_RARP
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366 #define CONFIG_CMD_PING
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367 /*#define CONFIG_CMD_SNTP */
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370 #define CONFIG_USB_CORE_IP_293A
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371 #define CONFIG_USB_GADGET_SC8800G
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372 #define CONFIG_USB_DWC
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373 #define CONFIG_USB_GADGET_DUALSPEED
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374 //#define CONFIG_USB_ETHER
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375 #define CONFIG_CMD_FASTBOOT
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376 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
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377 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
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378 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
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379 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
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381 #define CONFIG_MODEM_CALIBERATE
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385 #define CONFIG_SPLASH_SCREEN
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386 #define LCD_BPP LCD_COLOR16
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387 //#define CONFIG_LCD_HVGA 1
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388 //#define CONFIG_LCD_QVGA 1
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389 #define CONFIG_LCD_QHD 1
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390 //#define CONFIG_LCD_720P 1
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391 //#define CONFIG_LCD_INFO
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392 //#define LCD_TEST_PATTERN
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393 //#define CONFIG_LCD_LOGO
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394 //#define CONFIG_FB_LCD_S6D0139
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395 #define CONFIG_FB_LCD_SSD2075_MIPI
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396 #define CONFIG_FB_LCD_NT35516_MIPI
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397 #define CONFIG_SYS_WHITE_ON_BLACK
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398 #ifdef LCD_TEST_PATTERN
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399 #define CONSOLE_COLOR_RED 0xf800
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400 #define CONSOLE_COLOR_GREEN 0x07e0
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401 #define CONSOLE_COLOR_YELLOW 0x07e0
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402 #define CONSOLE_COLOR_BLUE 0x001f
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403 #define CONSOLE_COLOR_MAGENTA 0x001f
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404 #define CONSOLE_COLOR_CYAN 0x001f
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406 #endif // CONFIG_LCD
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408 #define CONFIG_SPRD_SYSDUMP
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409 #include <asm/sizes.h>
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411 #ifdef CONFIG_RAM512M
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412 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
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413 #elif defined(CONFIG_RAM256M)
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414 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_256M - 1))) + SZ_256M - SZ_1M)
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415 //#elif defined(CONFIG_RAMxxxM)
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416 //#define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_xxxM - 1))) + SZ_xxxM - SZ_1M) //xxx maybe 1024 etc
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418 #error "CONFIG_RAMxxxM macro must be defined"
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421 #define CALIBRATE_ENUM_MS 5000
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422 #define CALIBRATE_IO_MS 2000
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424 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
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425 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
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426 #define LOW_BAT_VOL_CHG 3200 //3.3V charger connect
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428 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
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429 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
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431 #define PHYS_OFFSET_ADDR 0x80000000
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432 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
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433 #define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
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434 //#define WCDMA_CP_OFFSET_ADDR 0x10000000 /*256M*/
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435 //#define WCDMA_CP_SDRAM_SIZE 0x4000000 /*64M*/
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436 #define WCN_CP_OFFSET_ADDR 0x14000000 /*320M*/
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437 #define WCN_CP_SDRAM_SIZE 0x281000//0x400000 /*4M*/
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439 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
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440 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
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441 #define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
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442 //#define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x93FFF000*/
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443 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x94EFF000*/
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445 #define CONFIG_RAM_CONSOLE
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447 #ifdef CONFIG_RAM_CONSOLE
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448 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
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449 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
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451 #define CALIBRATION_FLAG (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - 0x400) /*the last 1K of modem memory area*/
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452 #define CALIBRATION_FLAG_WCDMA CALIBRATION_FLAG
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453 //#define CALIBRATION_FLAG 0x89700000
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455 #define CONFIG_CMD_SOUND 1
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456 #define CONFIG_CMD_FOR_HTC 1
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457 #define CONFIG_SOUND_CODEC_SPRD_V3 1
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458 #define CONFIG_SOUND_DAI_VBC_R2P0 1
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459 /* #define CONFIG_SPRD_AUDIO_DEBUG */
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461 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
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462 #define USB_PHY_TUNE_VALUE 0x44073e33
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464 /*control the CP need to boot*/
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465 #define modem_cp0_enable 0
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466 #define modem_cp1_enable 1
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467 #define modem_cp2_enable 1
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469 #endif /* __CONFIG_H */
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