2 * (C) Copyright 2009 DENX Software Engineering
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3 * Author: John Rigby <jrigby@gmail.com>
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5 * This program is free software; you can redistribute it and/or
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6 * modify it under the terms of the GNU General Public License as
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7 * published by the Free Software Foundation; either version 2 of
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8 * the License, or (at your option) any later version.
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10 * This program is distributed in the hope that it will be useful,
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 * GNU General Public License for more details.
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15 * You should have received a copy of the GNU General Public License
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16 * along with this program; if not, write to the Free Software
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17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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23 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
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24 #define CONFIG_FDL2_PRINT 0
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25 #define BOOT_NATIVE_LINUX (0)
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27 #define CONFIG_SILENT_CONSOLE
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28 #define CONFIG_GPIOLIB 1
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29 //#define NAND_DEBUG
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31 #define U_BOOT_SPRD_VER 1
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32 /*#define SPRD_EVM_TAG_ON 1*/
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33 #ifdef SPRD_EVM_TAG_ON
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34 #define SPRD_EVM_ADDR_START 0x00026000
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35 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
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37 #define CONFIG_L2_OFF 1
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39 #define BOOT_DEBUG 1
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41 #define CONFIG_YAFFS2 1
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43 #define BOOT_PART "boot"
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44 //#define BOOT_PART "kernel"
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45 #define RECOVERY_PART "recovery"
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47 * SPREADTRUM BIGPHONE board - SoC Configuration
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49 #define CONFIG_SP8825
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50 #define CONFIG_SC8825
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51 #define CONFIG_TIGER
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52 #define CONFIG_SC8825EB
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55 #define CHIP_ENDIAN_LITTLE
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56 #define SC8800S_LITTLE_ENDIAN FALSE
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57 #define _LITTLE_ENDIAN 1
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58 #define EXT_MEM_TYPE_DDR 1
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62 /********** DDR timing configuration for customer begin *************/
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63 #define CONFIG_DDR_TIMING_CUSTOM FALSE //TRUE or FALSE
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65 // name: CONFIG_LPDDR1_DS
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66 // description: to config lpddr1 driver strength
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67 // note: when lpddr2, don't need to set this parameter
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76 #define CONFIG_LPDDR1_DS LPDDR1_DS_39_OHM
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78 // name: CONFIG_LPDDR2_DS
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79 // note: to config lpddr2 driver strength, when lpddr1, don't need to set this parameter
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86 #define CONFIG_LPDDR2_DS LPDDR2_DS_40_OHM
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88 // name: CONFIG_BYTEx_PHY_DLY
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89 // description: to config BYTE0~BYTE3 slave dll phase delay in ddr controller
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90 // note: when lpddr1, don't need to set this parameter
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100 #define CONFIG_BYTE0_PHS_DLY SDLL_PHS_DLY_DEF
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101 #define CONFIG_BYTE1_PHS_DLY SDLL_PHS_DLY_DEF
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102 #define CONFIG_BYTE2_PHS_DLY SDLL_PHS_DLY_DEF
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103 #define CONFIG_BYTE3_PHS_DLY SDLL_PHS_DLY_DEF
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105 // name: CONFIG_BYTEx_STEP_DLY
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106 // description: to config BYTE0~BYTE3 dqs step delay in ddr controller
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107 // note: when lpddr1, don't need to set this parameter
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109 // DQS_STEP_DLY_SUB3,
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110 // DQS_STEP_DLY_SUB2,
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111 // DQS_STEP_DLY_SUB1,
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112 // DQS_STEP_DLY_NOM,
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113 // DQS_STEP_DLY_DEF,
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114 // DQS_STEP_DLY_ADD1,
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115 // DQS_STEP_DLY_ADD2,
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116 // DQS_STEP_DLY_ADD3,
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117 // DQS_STEP_DLY_ADD4,
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118 #define CONFIG_BYTE0_STEP_DLY DQS_STEP_DLY_NOM
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119 #define CONFIG_BYTE1_STEP_DLY DQS_STEP_DLY_NOM
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120 #define CONFIG_BYTE2_STEP_DLY DQS_STEP_DLY_NOM
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121 #define CONFIG_BYTE3_STEP_DLY DQS_STEP_DLY_NOM
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122 /************* DDR timing configuration for customer end **************/
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125 #define CONFIG_EMMC_BOOT
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126 #define CONFIG_RAM512M
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129 #ifdef CONFIG_EMMC_BOOT
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130 #define EMMC_SECTOR_SIZE 512
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133 //#define CONFIG_TIGER_MMC
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134 #define CONFIG_UEFI_PARTITION
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135 #define CONFIG_EFI_PARTITION
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136 #define CONFIG_EXT4_SPARSE_DOWNLOAD
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137 //#define CONFIG_EMMC_SPL
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138 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM 0x400
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142 #define BB_DRAM_TYPE_256MB_32BIT
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143 #define CONFIG_MTD_NAND_TIGER 1
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144 //#define CONFIG_MTD_NAND_SC8810 1
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148 #define CONFIG_SYS_HZ 1000
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149 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
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151 //#define CONFIG_SYS_HUSH_PARSER
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153 #ifdef CONFIG_SYS_HUSH_PARSER
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154 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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157 #define FIXNV_SIZE (64 * 1024)
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158 #define MODEM_SIZE (0x800000)
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159 #define DSP_SIZE (0x3E0400) /* 3968K */
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160 #define VMJALUNA_SIZE (0x64000) /* 400K */
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161 #define RUNTIMENV_SIZE (256 * 1024)
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162 #define CONFIG_SPL_LOAD_LEN (0x6000)
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165 /*#define CMDLINE_NEED_CONV */
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167 #define WATCHDOG_LOAD_VALUE 0x4000
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168 #define CONFIG_SYS_STACK_SIZE 0x400
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169 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
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171 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
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173 /* NAND BOOT is the only boot method */
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174 #define CONFIG_NAND_U_BOOT
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175 #define DYNAMIC_CRC_TABLE
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176 /* Start copying real U-boot from the second page */
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177 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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178 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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179 #define RAM_TYPPE_IS_SDRAM 0
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180 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
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182 /* Load U-Boot to this address */
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183 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
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184 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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185 #define CONFIG_SYS_SDRAM_BASE 0x80000000
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186 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
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188 #ifdef CONFIG_NAND_SPL
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189 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
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192 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
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193 #define CONFIG_SYS_INIT_SP_ADDR \
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194 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
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196 #define CONFIG_SKIP_LOWLEVEL_INIT
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199 #define CONFIG_HW_WATCHDOG
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200 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
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201 //#define CONFIG_DISPLAY_CPUINFO
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203 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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204 #define CONFIG_SETUP_MEMORY_TAGS 1
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205 #define CONFIG_INITRD_TAG 1
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211 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
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213 * Board has 2 32MB banks of DRAM but there is a bug when using
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214 * both so only the first is configured
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216 #define CONFIG_NR_DRAM_BANKS 1
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218 #define PHYS_SDRAM_1 0x80000000
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219 #define PHYS_SDRAM_1_SIZE 0x10000000
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220 #if (CONFIG_NR_DRAM_BANKS == 2)
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221 #define PHYS_SDRAM_2 0x90000000
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222 #define PHYS_SDRAM_2_SIZE 0x10000000
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224 /* 8MB DRAM test */
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225 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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226 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
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227 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
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232 #define CONFIG_SPRD_UART 1
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233 #define CONFIG_SYS_SC8800X_UART1 1
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234 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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235 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
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236 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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237 #define CONFIG_SC8825_SPI
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238 #define CONFIG_SC8825_I2C
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240 * Flash & Environment
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242 /* No NOR flash present */
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243 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
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244 #define CONFIG_SYS_NO_FLASH 1
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245 #define CONFIG_ENV_IS_NOWHERE
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246 #define CONFIG_ENV_SIZE (128 * 1024)
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248 #define CONFIG_ENV_IS_IN_NAND
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249 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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250 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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254 #define CONFIG_NAND_TIGER
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255 //#define CONFIG_NAND_SC8810
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256 #define CONFIG_SPRD_NAND_REGS_BASE (0x21100000)
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257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
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258 #define CONFIG_SYS_NAND_BASE (0x21100000)
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259 //#define CONFIG_JFFS2_NAND
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260 //#define CONFIG_SPRD_NAND_HWECC
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261 #define CONFIG_SYS_NAND_HW_ECC
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262 #define CONFIG_SYS_NAND_LARGEPAGE
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263 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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265 #define CONFIG_SYS_64BIT_VSPRINTF
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267 #define CONFIG_CMD_MTDPARTS
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268 #define CONFIG_MTD_PARTITIONS
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269 #define CONFIG_MTD_DEVICE
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270 #define CONFIG_CMD_UBI
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271 #define CONFIG_RBTREE
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273 /* U-Boot general configuration */
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274 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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275 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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276 /* Print buffer sz */
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277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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278 sizeof(CONFIG_SYS_PROMPT) + 16)
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279 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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280 /* Boot Argument Buffer Size */
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281 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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282 #define CONFIG_CMDLINE_EDITING
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283 #define CONFIG_SYS_LONGHELP
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285 /* support OS choose */
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286 #undef CONFIG_BOOTM_NETBSD
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287 #undef CONFIG_BOOTM_RTEMS
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289 /* U-Boot commands */
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290 #include <config_cmd_default.h>
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291 #define CONFIG_CMD_NAND
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292 #undef CONFIG_CMD_FPGA
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293 #undef CONFIG_CMD_LOADS
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294 #undef CONFIG_CMD_NET
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295 #undef CONFIG_CMD_NFS
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296 #undef CONFIG_CMD_SETGETDCR
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298 #define CONFIG_ENV_OVERWRITE
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300 #ifdef SPRD_EVM_TAG_ON
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301 #define CONFIG_BOOTDELAY 0
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303 #define CONFIG_BOOTDELAY 0
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304 #define CONFIG_ZERO_BOOTDELAY_CHECK
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307 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
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308 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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310 #define xstr(s) str(s)
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313 #define MTDIDS_DEFAULT "nand0=sprd-nand"
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314 #ifdef CONFIG_G2PHONE
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315 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:384k@256k(boot),256k(params),6m(kernel),6m(ramdisk),6m(recovery),70m(system),30m(userdata),7m(cache)"
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316 #define CONFIG_BOOTARGS "mem=64M console=ttyS1,115200n8 init=/init "MTDPARTS_DEFAULT
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317 #elif defined CONFIG_SC8825
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318 /*#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),384k(2ndbl),128k(params),512k(vmjaluna),6016k(modem),7680k(kernel),5120k(dsp),1280k(fixnv),2560k(runtimenv),6400k(recovery),100m(system),198m(userdata),1m(boot_logo),1m(fastboot_logo),2m(cache),256k(misc)"*/
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319 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),128k(params),512k(vmjaluna),10m(modem),10m(boot),5120k(dsp),1280k(fixnv),3840k(backupfixnv),3840k(runtimenv),10m(recovery),150m(system),300m(userdata),1m(boot_logo),1m(fastboot_logo),2m(cache),256k(misc)"
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320 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),128k(params),512k(vmjaluna),10m(modem),10m(boot)"
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321 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
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322 #define CONFIG_BOOTARGS "mem=256M console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
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325 #define COPY_LINUX_KERNEL_SIZE (0x600000)
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326 #define LINUX_INITRD_NAME "modem"
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328 #define CONFIG_BOOTCOMMAND "cboot normal"
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329 #define CONFIG_EXTRA_ENV_SETTINGS ""
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331 #ifdef CONFIG_CMD_NET
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332 #define CONFIG_IPADDR 192.168.10.2
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333 #define CONFIG_SERVERIP 192.168.10.5
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334 #define CONFIG_NETMASK 255.255.255.0
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335 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
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336 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
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339 #define CONFIG_NET_MULTI
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340 #define CONFIG_CMD_DNS
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341 #define CONFIG_CMD_NFS
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342 #define CONFIG_CMD_RARP
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343 #define CONFIG_CMD_PING
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344 /*#define CONFIG_CMD_SNTP */
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347 #define CONFIG_USB_CORE_IP_293A
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348 #define CONFIG_USB_GADGET_SC8800G
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349 #define CONFIG_USB_DWC
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350 #define CONFIG_USB_GADGET_DUALSPEED
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351 //#define CONFIG_USB_ETHER
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352 #define CONFIG_CMD_FASTBOOT
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353 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
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354 #define FB_DOWNLOAD_BUF_SIZE (250*1024*1024)
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356 #define CONFIG_MODEM_CALIBERATE
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358 #define CONFIG_UPDATE_TFTP
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360 #define CONFIG_OF_LIBFDT
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361 #define CONFIG_SYS_MAX_FLASH_BANKS 1
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362 #define CONFIG_SYS_MAX_FLASH_SECT 128
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366 #define CONFIG_SPLASH_SCREEN
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367 #define LCD_BPP LCD_COLOR16
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368 //#define CONFIG_LCD_HVGA 1
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369 //#define CONFIG_LCD_WVGA 1
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370 #define CONFIG_LCD_QHD 1
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371 //#define CONFIG_LCD_INFO
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372 //#define LCD_TEST_PATTERN
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373 //#define CONFIG_LCD_LOGO
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374 #define CONFIG_FB_LCD_NT35516_MCU
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375 //#define CONFIG_FB_LCD_HX8362_RGB_SPI
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376 #define CONFIG_SYS_WHITE_ON_BLACK
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377 #ifdef LCD_TEST_PATTERN
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378 #define CONSOLE_COLOR_RED 0xf800
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379 #define CONSOLE_COLOR_GREEN 0x07e0
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380 #define CONSOLE_COLOR_YELLOW 0x07e0
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381 #define CONSOLE_COLOR_BLUE 0x001f
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382 #define CONSOLE_COLOR_MAGENTA 0x001f
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383 #define CONSOLE_COLOR_CYAN 0x001f
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385 #endif // CONFIG_LCD
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390 #define CONFIG_CMD_MMC
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391 #ifdef CONFIG_CMD_MMC
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392 #define CONFIG_CMD_FAT 1
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393 #define CONFIG_FAT_WRITE 1
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394 #define CONFIG_GENERIC_MMC 1
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395 #define CONFIG_SDHCI 1
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396 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
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397 #define CONFIG_MMC_SDMA 1
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398 #define CONFIG_MV_SDHCI 1
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399 #define CONFIG_DOS_PARTITION 1
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400 #define CONFIG_SYS_MMC_NUM 2
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401 #define CONFIG_SYS_MMC_BASE {0x20510000,0x20530000}
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404 #define CALIBRATE_ENUM_MS 15000
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405 #define CALIBRATE_IO_MS 10000
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407 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
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408 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
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409 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
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411 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
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412 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
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413 #define USB_PHY_TUNE_VALUE 0x44073e33
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415 #endif /* __CONFIG_H */
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