2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
24 #define CONFIG_FDL2_PRINT 0
25 #define BOOT_NATIVE_LINUX 1
26 #define BOOT_NATIVE_LINUX_MODEM 1
27 //#define CALIBRATION_FLAG 0x897FFC00
28 //#define CALIBRATION_FLAG_WCDMA 0x897FFC00
29 #define CONFIG_SILENT_CONSOLE
30 #define CONFIG_GPIOLIB 1
33 #define CONFIG_SDRAMDISK
35 #define U_BOOT_SPRD_VER 1
36 /*#define SPRD_EVM_TAG_ON 1*/
37 #ifdef SPRD_EVM_TAG_ON
38 #define SPRD_EVM_ADDR_START 0x00026000
39 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
41 #define CONFIG_L2_OFF 1
45 #define CONFIG_YAFFS2 1
47 #define BOOT_PART "boot"
48 //#define BOOT_PART "kernel"
49 #define RECOVERY_PART "recovery"
50 #define UBIPAC_PART "ubipac"
53 * SPREADTRUM BIGPHONE board - SoC Configuration
56 #define CONFIG_SPX15_TD
59 #define CONFIG_AUTODLOADER
60 #define CONFIG_SP8830WCN
63 #define CONFIG_SUPPORT_TD
64 #define TDDSP_ADR 0x88020000
65 #define TDFIXNV_ADR 0x89060000
66 #define TDRUNTIMENV_ADR 0x890a0000
67 #define TDMODEM_ADR 0x88300000
69 #define CONFIG_SUPPORT_WIFI
70 #define WCNMODEM_ADR 0x8a860000
71 #define WCNFIXNV_ADR 0x8a800000
72 #define WCNRUNTIMENV_ADR 0x8a820000
73 #define CHIP_ENDIAN_LITTLE
74 #define _LITTLE_ENDIAN 1
76 //#define CONFIG_RAM512M
77 #define CONFIG_RAM256M
79 //#define CONFIG_EMMC_BOOT
81 #ifdef CONFIG_EMMC_BOOT
82 #define EMMC_SECTOR_SIZE 512
85 #define CONFIG_FS_EXT4
86 #define CONFIG_EXT4_WRITE
87 #define CONFIG_CMD_EXT4
88 #define CONFIG_CMD_EXT4_WRITE
90 //#define CONFIG_TIGER_MMC
91 #define CONFIG_UEFI_PARTITION
92 #define CONFIG_EFI_PARTITION
93 #define CONFIG_EXT4_SPARSE_DOWNLOAD
94 //#define CONFIG_EMMC_SPL
95 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
101 #define CONFIG_CMD_MMC
102 #ifdef CONFIG_CMD_MMC
103 #define CONFIG_CMD_FAT 1
104 #define CONFIG_FAT_WRITE 1
106 #define CONFIG_GENERIC_MMC 1
107 #define CONFIG_SDHCI 1
108 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
109 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
110 #define CONFIG_MMC_SDMA 1
111 #define CONFIG_MV_SDHCI 1
112 #define CONFIG_DOS_PARTITION 1
113 #define CONFIG_EFI_PARTITION 1
114 #define CONFIG_SYS_MMC_NUM 1
115 #define CONFIG_SYS_MMC_BASE {0x20600000}
116 #define CONFIG_SYS_SD_BASE 0x20300000
119 #define BB_DRAM_TYPE_256MB_32BIT
121 #define CONFIG_SYS_HZ 1000
122 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
124 //#define CONFIG_SYS_HUSH_PARSER
126 #ifdef CONFIG_SYS_HUSH_PARSER
127 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
130 #define FIXNV_SIZE (256 * 1024)
131 #define TDMODEM_SIZE (0x600000)
132 #define TDDSP_SIZE (0x2E0000)
133 #define WCNMODEM_SIZE (0x100000)
134 #define VMJALUNA_SIZE (0x64000) /* 400K */
135 #define RUNTIMENV_SIZE (384 * 1024)
136 #define CONFIG_SPL_LOAD_LEN (0x6000)
139 /*#define CMDLINE_NEED_CONV */
141 #define WATCHDOG_LOAD_VALUE 0x4000
142 #define CONFIG_SYS_STACK_SIZE 0x400
143 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
145 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
147 /* NAND BOOT is the only boot method */
148 #define CONFIG_NAND_U_BOOT
149 #define DYNAMIC_CRC_TABLE
150 /* Start copying real U-boot from the second page */
151 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
152 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
153 #define RAM_TYPPE_IS_SDRAM 0
154 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
156 /* Load U-Boot to this address */
157 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
158 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
159 #define CONFIG_SYS_SDRAM_BASE 0x80000000
160 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
162 #ifdef CONFIG_NAND_SPL
163 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
166 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
167 #define CONFIG_SYS_INIT_SP_ADDR \
168 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
170 #define CONFIG_SKIP_LOWLEVEL_INIT
173 #define CONFIG_HW_WATCHDOG
174 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
175 //#define CONFIG_DISPLAY_CPUINFO
177 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
178 #define CONFIG_SETUP_MEMORY_TAGS 1
179 #define CONFIG_INITRD_TAG 1
185 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
187 * Board has 2 32MB banks of DRAM but there is a bug when using
188 * both so only the first is configured
190 #define CONFIG_NR_DRAM_BANKS 1
192 #define PHYS_SDRAM_1 0x80000000
193 #define PHYS_SDRAM_1_SIZE 0x10000000
194 #if (CONFIG_NR_DRAM_BANKS == 2)
195 #define PHYS_SDRAM_2 0x90000000
196 #define PHYS_SDRAM_2_SIZE 0x10000000
199 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
200 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
201 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
206 #define CONFIG_SPRD_UART 1
207 #define CONFIG_SYS_SC8800X_UART1 1
208 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
209 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
210 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
211 #define CONFIG_SPRD_SPI
212 #define CONFIG_SPRD_I2C
213 #define CONFIG_SC8830_I2C
215 * Flash & Environment
217 /* No NOR flash present */
218 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
219 #define CONFIG_SYS_NO_FLASH 1
220 #define CONFIG_ENV_IS_NOWHERE
221 #define CONFIG_ENV_SIZE (128 * 1024)
223 #define CONFIG_ENV_IS_IN_NAND
224 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
225 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
229 #define CONFIG_CLK_PARA
230 //#define CONFIG_FPGA
232 #ifndef CONFIG_CLK_PARA
235 #define MAGIC_HEADER 0x5555AAAA
236 #define MAGIC_END 0xAAAA5555
237 #define CONFIG_PARA_VERSION 1
238 #define CLK_CA7_CORE ARM_CLK_1000M
239 #define CLK_CA7_AXI ARM_CLK_500M
240 #define CLK_CA7_DGB ARM_CLK_200M
241 #define CLK_CA7_AHB AHB_CLK_192M
242 #define CLK_CA7_APB APB_CLK_64M
243 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
244 #define CLK_AON_APB AON_APB_CLK_128M
245 #define DDR_FREQ 333000000
246 #define DCDC_ARM 1200
247 #define DCDC_CORE 1100
248 #define CONFIG_VOL_PARA
250 //---these three macro below,only one can be open
255 //#define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
256 //#define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
257 #define DDR_TYPE DRAM_LPDDR2_1CS_2G_X32
258 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
259 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
260 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
261 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
263 #define DDR3_DLL_ON TRUE
265 #define DDR_APB_CLK 128
266 #define DDR_DFS_SUPPORT
267 #define DDR_DFS_VAL_BASE 0X1c00
269 //#define DDR_SCAN_SUPPORT
270 #define MEM_IO_DS LPDDR2_DS_40R
272 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
273 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
274 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
277 #define CONFIG_NAND_DOLPHIN
278 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
279 #define CONFIG_SYS_MAX_NAND_DEVICE 1
280 #define CONFIG_SYS_NAND_BASE (0x20B00000)
281 //#define CONFIG_JFFS2_NAND
282 //#define CONFIG_SPRD_NAND_HWECC
283 #define CONFIG_SYS_NAND_HW_ECC
284 #define CONFIG_SYS_NAND_LARGEPAGE
285 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
287 #define CONFIG_SYS_64BIT_VSPRINTF
289 #define CONFIG_CMD_MTDPARTS
290 #define CONFIG_MTD_PARTITIONS
291 #define CONFIG_MTD_DEVICE
292 #define CONFIG_CMD_UBI
293 #define CONFIG_RBTREE
294 #define CONFIG_CMD_UBIFS
296 #ifdef CONFIG_CMD_UBIFS
297 #define CONFIG_FS_UBIFS
299 /* U-Boot general configuration */
300 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
301 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
302 /* Print buffer sz */
303 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
304 sizeof(CONFIG_SYS_PROMPT) + 16)
305 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
306 /* Boot Argument Buffer Size */
307 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
308 #define CONFIG_CMDLINE_EDITING
309 #define CONFIG_SYS_LONGHELP
311 /* support OS choose */
312 #undef CONFIG_BOOTM_NETBSD
313 #undef CONFIG_BOOTM_RTEMS
315 /* U-Boot commands */
316 #include <config_cmd_default.h>
317 #define CONFIG_CMD_NAND
318 #undef CONFIG_CMD_FPGA
319 #undef CONFIG_CMD_LOADS
320 #undef CONFIG_CMD_NET
321 #undef CONFIG_CMD_NFS
322 #undef CONFIG_CMD_SETGETDCR
324 #define CONFIG_ENV_OVERWRITE
326 #ifdef SPRD_EVM_TAG_ON
327 #define CONFIG_BOOTDELAY 0
329 #define CONFIG_BOOTDELAY 0
330 #define CONFIG_ZERO_BOOTDELAY_CHECK
333 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
334 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
336 #define xstr(s) str(s)
339 #ifdef CONFIG_RAM512M
340 #define MEM_INIT_PARA "mem=512M"
341 #elif defined(CONFIG_RAM256M)
342 #define MEM_INIT_PARA "mem=256M"
343 //#elif defined(CONFIG_RAMxxxM)
344 ////#define MEM_INIT_PARA "mem=xxxM" //xxx maybe 1024 etc
346 #error "CONFIG_RAMxxxM macro must be defined"
348 #define MTDIDS_DEFAULT "nand0=sprd-nand"
349 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),2m(2ndbl),256k(tdmodem),256k(tddsp),256k(tdfixnv1),256k(tdruntimenv),256k(wmodem),256k(wdsp),256k(wfixnv1),256k(wruntimenv1),256k(prodinfo1),256k(prodinfo3),1024k(logo),1024k(fastbootlogo),10m(boot),300m(system),150m(cache),10m(recovery),256k(misc),256k(sd),512k(userdata)"
350 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),768k(2ndbl),512k(kpanic),-(ubipac)"
351 #define CONFIG_BOOTARGS MEM_INIT_PARA" loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
352 #define COPY_LINUX_KERNEL_SIZE (0x600000)
353 #define LINUX_INITRD_NAME "modem"
355 #define CONFIG_BOOTCOMMAND "cboot normal"
356 #define CONFIG_EXTRA_ENV_SETTINGS ""
358 #ifdef CONFIG_CMD_NET
359 #define CONFIG_IPADDR 192.168.10.2
360 #define CONFIG_SERVERIP 192.168.10.5
361 #define CONFIG_NETMASK 255.255.255.0
362 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
363 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
366 #define CONFIG_NET_MULTI
367 #define CONFIG_CMD_DNS
368 #define CONFIG_CMD_NFS
369 #define CONFIG_CMD_RARP
370 #define CONFIG_CMD_PING
371 /*#define CONFIG_CMD_SNTP */
374 #define CONFIG_USB_CORE_IP_293A
375 #define CONFIG_USB_GADGET_SC8800G
376 #define CONFIG_USB_DWC
377 #define CONFIG_USB_GADGET_DUALSPEED
378 //#define CONFIG_USB_ETHER
379 #define CONFIG_CMD_FASTBOOT
380 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
381 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
382 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
383 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
385 #define CONFIG_MODEM_CALIBERATE
389 #define CONFIG_SPLASH_SCREEN
390 #define LCD_BPP LCD_COLOR16
391 //#define CONFIG_LCD_HVGA 1
392 //#define CONFIG_LCD_QVGA 1
393 //#define CONFIG_LCD_QHD 1
394 //#define CONFIG_LCD_720P 1
395 #define CONFIG_LCD_FWVGA 1
397 //#define CONFIG_LCD_INFO
398 //#define LCD_TEST_PATTERN
399 //#define CONFIG_LCD_LOGO
400 //#define CONFIG_FB_LCD_S6D0139
401 //#define CONFIG_FB_LCD_SSD2075_MIPI
402 //#define CONFIG_FB_LCD_NT35516_MIPI
403 #define CONFIG_FB_LCD_HX8363_RGB_SPI
404 //#define CONFIG_FB_LCD_HX8363_MCU
406 #define CONFIG_SYS_WHITE_ON_BLACK
407 #ifdef LCD_TEST_PATTERN
408 #define CONSOLE_COLOR_RED 0xf800
409 #define CONSOLE_COLOR_GREEN 0x07e0
410 #define CONSOLE_COLOR_YELLOW 0x07e0
411 #define CONSOLE_COLOR_BLUE 0x001f
412 #define CONSOLE_COLOR_MAGENTA 0x001f
413 #define CONSOLE_COLOR_CYAN 0x001f
417 #define CONFIG_SPRD_SYSDUMP
418 #include <asm/sizes.h>
420 #ifdef CONFIG_RAM512M
421 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
422 #elif defined(CONFIG_RAM256M)
423 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_256M - 1))) + SZ_256M - SZ_1M)
424 //#elif defined(CONFIG_RAMxxxM)
425 //#define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_xxxM - 1))) + SZ_xxxM - SZ_1M) //xxx maybe 1024 etc
427 #error "CONFIG_RAMxxxM macro must be defined"
430 #define CALIBRATE_ENUM_MS 3000
431 #define CALIBRATE_IO_MS 2000
433 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
434 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
435 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
437 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
438 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
440 #define PHYS_OFFSET_ADDR 0x80000000
441 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
442 #define TD_CP_SDRAM_SIZE 0x1200000 /*24M*/
443 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*128M*/
444 #define WCDMA_CP_SDRAM_SIZE 0x2000000 /*32M*/
446 #define WCN_CP_OFFSET_ADDR 0xa800000 /*168M*/
447 #define WCN_CP_SDRAM_SIZE 0x281000//0x500000 /*5M*/
449 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
450 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
451 #define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
452 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
453 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
455 #define CALIBRATION_FLAG (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - 0x400) /*the last 1K of modem memory area*/
456 #define CALIBRATION_FLAG_WCDMA CALIBRATION_FLAG
457 //#define CALIBRATION_FLAG 0x89700000
459 #define CONFIG_CMD_SOUND 1
460 #define CONFIG_CMD_FOR_HTC 1
461 #define CONFIG_SOUND_CODEC_SPRD_V3 1
462 #define CONFIG_SOUND_DAI_VBC_R2P0 1
463 /* #define CONFIG_SPRD_AUDIO_DEBUG */
465 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
467 #define CONFIG_PBINT_7S_RESET_V1
468 /* short reset when power key reset trigged */
469 #define CONFIG_PBINT_7S_RST_SW_SHORT 1
470 /* reset then release the power key when reset trigged */
471 /* #define CONFIG_PBINT_7S_RST_SW_LONG 1 */
472 /* reset then release the power key when reset trigged */
473 /* #define CONFIG_PBINT_7S_RST_HW_LONG 1 */
474 /* rang:2-16 unit: s */
475 /* #define CONFIG_PBINT_7S_RST_THRESHOLD 7 */
477 /* #define CONFIG_SMPL_MODE */
478 /* rang:0(0.5s) - 7(4s) unit: s step: 0.5s */
479 /* #define CONFIG_SMPL_THRESHOLD 0 */
481 #endif /* __CONFIG_H */