2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 //#define CONFIG_SECURE_BOOT
25 //#define CONFIG_ROM_VERIFY_SPL
26 #define PRIMPUKPATH "/dev/block/mmcblk0boot0"
27 #define PRIMPUKSTART 512
28 #define PRIMPUKLEN 260
29 //#define CONFIG_OF_LIBFDT
30 //#ifdef CONFIG_OF_LIBFDT
31 //MACH_TYPE_SC8830=2014
33 #define DT_PLATFROM_ID 8830
34 #define DT_HARDWARE_ID 1
35 #define DT_SOC_VER 0x20000
37 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
38 #define CONFIG_FDL2_PRINT 0
39 #define BOOT_NATIVE_LINUX 1
40 #define BOOT_NATIVE_LINUX_MODEM 1
41 #define CONFIG_SILENT_CONSOLE
42 #define CONFIG_GPIOLIB 1
45 #define U_BOOT_SPRD_VER 1
46 /*#define SPRD_EVM_TAG_ON 1*/
47 #ifdef SPRD_EVM_TAG_ON
48 #define SPRD_EVM_ADDR_START 0x00026000
49 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
51 #define CONFIG_L2_OFF 1
55 #define CONFIG_YAFFS2 1
57 #define BOOT_PART "boot"
58 //#define BOOT_PART "kernel"
59 #define RECOVERY_PART "recovery"
60 #define UBIPAC_PART "ubipac"
63 * SPREADTRUM BIGPHONE board - SoC Configuration
69 #define CONFIG_SP7731GEA_HD
70 #define CONFIG_SP8830WCN
71 #define CONFIG_ADIE_SC2713S
73 #define CONFIG_SUPPORT_W
74 #define WDSP_ADR 0x88020000
75 #define WFIXNV_ADR 0x88240000
76 #define WRUNTIMENV_ADR 0x88280000
77 #define WMODEM_ADR 0x88300000
78 #define MODEM_ADR WMODEM_ADR
79 #define CONFIG_SUPPORT_WIFI
80 #define WCNMODEM_ADR 0x8a808000
81 #define WCNFIXNV_ADR 0x8a800000
82 #define WCNRUNTIMENV_ADR 0x8a820000
83 #define CP0_CODE_COPY_ADR 0x50000000
84 #define CP2_CODE_COPY_ADR 0x50003000
86 #define CONFIG_AUTODLOADER
88 #define CHIP_ENDIAN_LITTLE
89 #define _LITTLE_ENDIAN 1
93 #define CONFIG_EMMC_BOOT
95 #ifdef CONFIG_EMMC_BOOT
96 #define EMMC_SECTOR_SIZE 512
99 #define CONFIG_FS_EXT4
100 #define CONFIG_EXT4_WRITE
101 #define CONFIG_CMD_EXT4
102 #define CONFIG_CMD_EXT4_WRITE
104 //#define CONFIG_TIGER_MMC
105 #define CONFIG_UEFI_PARTITION
106 #define CONFIG_EFI_PARTITION
107 #define CONFIG_EXT4_SPARSE_DOWNLOAD
108 //#define CONFIG_EMMC_SPL
109 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
116 #define CONFIG_CMD_MMC
117 #ifdef CONFIG_CMD_MMC
118 #define CONFIG_CMD_FAT 1
119 #define CONFIG_FAT_WRITE 1
121 #define CONFIG_GENERIC_MMC 1
122 #define CONFIG_SDHCI 1
123 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
124 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
125 #define CONFIG_MMC_SDMA 1
126 #define CONFIG_MV_SDHCI 1
127 #define CONFIG_DOS_PARTITION 1
128 #define CONFIG_EFI_PARTITION 1
129 #define CONFIG_SYS_MMC_NUM 1
130 #define CONFIG_SYS_MMC_BASE {0x20600000}
131 #define CONFIG_SYS_SD_BASE 0x20300000
134 #define BB_DRAM_TYPE_256MB_32BIT
136 #define CONFIG_SYS_HZ 1000
137 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
139 //#define CONFIG_SYS_HUSH_PARSER
141 #ifdef CONFIG_SYS_HUSH_PARSER
142 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
145 #define FIXNV_SIZE (2*128 * 1024)
146 #define PRODUCTINFO_SIZE (16 * 1024)
147 #define WMODEM_SIZE (0x800000)
148 #define WDSP_SIZE (0x200000)
149 #define WCNMODEM_SIZE (0x100000)
150 #define VMJALUNA_SIZE (0x64000) /* 400K */
151 #define RUNTIMENV_SIZE (3*128 * 1024)
152 #ifdef CONFIG_ROM_VERIFY_SPL
153 #define CONFIG_SPL_LOAD_LEN (0x8000) /* 32 KB */
154 #define CONFIG_BOOTINFO_LENGTH (0x200) /* 512 Bytes*/
155 #define PUBKEY_BSC_BLOCK_INDEX (CONFIG_SPL_LOAD_LEN - CONFIG_BOOTINFO_LENGTH * 2) / EMMC_SECTOR_SIZE
156 #define PUBKEY_VLR_BLOCK_INDEX 2
157 #define PUBKEY_READ_BLOCK_NUMS 1
158 #define CONFIG_SPL_HASH_LEN (0x400) /* 1KB */
160 #define CONFIG_SPL_LOAD_LEN (0x6000)
161 #define PUBKEY_BSC_BLOCK_INDEX 0
162 #define PUBKEY_VLR_BLOCK_INDEX 0
163 #define PUBKEY_READ_BLOCK_NUMS (SEC_HEADER_MAX_SIZE / EMMC_SECTOR_SIZE)
164 #define CONFIG_SPL_HASH_LEN (0xC00) /* 3KB */
167 #define PRODUCTINFO_ADR 0x80490000
169 /*#define CMDLINE_NEED_CONV */
171 #define WATCHDOG_LOAD_VALUE 0x4000
172 #define CONFIG_SYS_STACK_SIZE 0x400
173 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
175 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
177 /* NAND BOOT is the only boot method */
178 #define CONFIG_NAND_U_BOOT
179 #define DYNAMIC_CRC_TABLE
180 /* Start copying real U-boot from the second page */
181 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
182 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
183 #define RAM_TYPPE_IS_SDRAM 0
184 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
186 /* Load U-Boot to this address */
187 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f700000
188 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
189 #define CONFIG_SYS_SDRAM_BASE 0x80000000
190 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
192 #ifdef CONFIG_NAND_SPL
193 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
196 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
197 #define CONFIG_SYS_INIT_SP_ADDR \
198 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SKIP_LOWLEVEL_INIT
203 #define CONFIG_HW_WATCHDOG
204 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
205 //#define CONFIG_DISPLAY_CPUINFO
207 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
208 #define CONFIG_SETUP_MEMORY_TAGS 1
209 #define CONFIG_INITRD_TAG 1
215 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
217 * Board has 2 32MB banks of DRAM but there is a bug when using
218 * both so only the first is configured
220 #define CONFIG_NR_DRAM_BANKS 1
222 #define PHYS_SDRAM_1 0x80000000
223 #define PHYS_SDRAM_1_SIZE 0x10000000
224 #if (CONFIG_NR_DRAM_BANKS == 2)
225 #define PHYS_SDRAM_2 0x90000000
226 #define PHYS_SDRAM_2_SIZE 0x10000000
229 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
230 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
231 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
236 #define CONFIG_SPRD_UART 1
237 #define CONFIG_SYS_SC8800X_UART1 1
238 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
239 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
240 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
241 #define CONFIG_SPRD_SPI
242 #define CONFIG_SPRD_I2C
243 #define CONFIG_SC8830_I2C
245 * Flash & Environment
247 /* No NOR flash present */
248 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
249 #define CONFIG_SYS_NO_FLASH 1
250 #define CONFIG_ENV_IS_NOWHERE
251 #define CONFIG_ENV_SIZE (128 * 1024)
253 #define CONFIG_ENV_IS_IN_NAND
254 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
255 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
259 #define CONFIG_CLK_PARA
261 #ifndef CONFIG_CLK_PARA
264 #define MAGIC_HEADER 0x5555AAAA
265 #define MAGIC_END 0xAAAA5555
266 #define CONFIG_PARA_VERSION 1
267 #define CLK_CA7_CORE ARM_CLK_1000M
268 #define CLK_CA7_AXI ARM_CLK_500M
269 #define CLK_CA7_DGB ARM_CLK_200M
270 #define CLK_CA7_AHB AHB_CLK_192M
271 #define CLK_CA7_APB APB_CLK_64M
272 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
273 #define CLK_AON_APB AON_APB_CLK_128M
274 #define DDR_FREQ 800000000
275 #define DCDC_ARM 1200
276 #define DCDC_CORE 1100
277 #define CONFIG_VOL_PARA
282 #define CONFIG_NAND_SC8830
283 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
284 #define CONFIG_SYS_MAX_NAND_DEVICE 1
285 #define CONFIG_SYS_NAND_BASE (0x20B00000)
286 //#define CONFIG_JFFS2_NAND
287 //#define CONFIG_SPRD_NAND_HWECC
288 #define CONFIG_SYS_NAND_HW_ECC
289 #define CONFIG_SYS_NAND_LARGEPAGE
290 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
292 #define CONFIG_SYS_64BIT_VSPRINTF
294 #define CONFIG_CMD_MTDPARTS
295 #define CONFIG_MTD_PARTITIONS
296 #define CONFIG_MTD_DEVICE
297 #define CONFIG_CMD_UBI
298 #define CONFIG_RBTREE
300 #define CONFIG_CMD_UBIFS
302 #ifdef CONFIG_CMD_UBIFS
303 #define CONFIG_FS_UBIFS
306 /* U-Boot general configuration */
307 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
308 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
309 /* Print buffer sz */
310 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
311 sizeof(CONFIG_SYS_PROMPT) + 16)
312 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
313 /* Boot Argument Buffer Size */
314 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
315 #define CONFIG_CMDLINE_EDITING
316 #define CONFIG_SYS_LONGHELP
318 /* support OS choose */
319 #undef CONFIG_BOOTM_NETBSD
320 #undef CONFIG_BOOTM_RTEMS
322 /* U-Boot commands */
323 #include <config_cmd_default.h>
324 #define CONFIG_CMD_NAND
325 #undef CONFIG_CMD_FPGA
326 #undef CONFIG_CMD_LOADS
327 #undef CONFIG_CMD_NET
328 #undef CONFIG_CMD_NFS
329 #undef CONFIG_CMD_SETGETDCR
331 #define CONFIG_ENV_OVERWRITE
333 #ifdef SPRD_EVM_TAG_ON
334 #define CONFIG_BOOTDELAY 0
336 #define CONFIG_BOOTDELAY 0
337 #define CONFIG_ZERO_BOOTDELAY_CHECK
340 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
341 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
343 #define xstr(s) str(s)
347 #define MEM_INIT_PARA "mem=1024M"
348 #elif defined(CONFIG_RAM512M)
349 #define MEM_INIT_PARA "mem=512M"
350 #elif defined(CONFIG_RAM256M)
351 #define MEM_INIT_PARA "mem=256M"
352 //#elif defined(CONFIG_RAMxxxM)
353 ////#define MEM_INIT_PARA "mem=xxxM" //xxx maybe 1024 etc
355 #error "CONFIG_RAMxxxM macro must be defined"
357 #define MTDIDS_DEFAULT "nand0=sprd-nand"
358 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
359 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),768k(2ndbl),512k(kpanic),-(ubipac)"
360 #define CONFIG_BOOTARGS MEM_INIT_PARA" loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
362 #define COPY_LINUX_KERNEL_SIZE (0x600000)
363 #define LINUX_INITRD_NAME "modem"
365 #define CONFIG_BOOTCOMMAND "cboot normal"
366 #define CONFIG_EXTRA_ENV_SETTINGS ""
368 #ifdef CONFIG_CMD_NET
369 #define CONFIG_IPADDR 192.168.10.2
370 #define CONFIG_SERVERIP 192.168.10.5
371 #define CONFIG_NETMASK 255.255.255.0
372 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
373 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
376 #define CONFIG_NET_MULTI
377 #define CONFIG_CMD_DNS
378 #define CONFIG_CMD_NFS
379 #define CONFIG_CMD_RARP
380 #define CONFIG_CMD_PING
381 /*#define CONFIG_CMD_SNTP */
384 #define CONFIG_USB_CORE_IP_293A
385 #define CONFIG_USB_GADGET_SC8800G
386 #define CONFIG_USB_DWC
387 #define CONFIG_USB_GADGET_DUALSPEED
388 //#define CONFIG_USB_ETHER
389 #define CONFIG_CMD_FASTBOOT
390 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
391 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
392 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
393 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
395 #define CONFIG_MODEM_CALIBERATE
399 #define CONFIG_DSIH_VERSION_1P21A
400 #define CONFIG_SPLASH_SCREEN
401 #define LCD_BPP LCD_COLOR16
402 //#define CONFIG_LCD_HVGA 1
403 //#define CONFIG_LCD_QVGA 1
404 //#define CONFIG_LCD_QHD 1
405 //#define CONFIG_LCD_720P 1
406 #define CONFIG_LCD_FWVGA 1
407 //#define CONFIG_LCD_INFO
408 //#define LCD_TEST_PATTERN
409 //#define CONFIG_LCD_LOGO
410 //#define CONFIG_FB_LCD_S6D0139
411 #define CONFIG_FB_LCD_SSD2075_MIPI
412 #define CONFIG_FB_LOW_RES_SIMU
413 #ifdef CONFIG_FB_LOW_RES_SIMU
414 #define LCD_DISPLAY_WIDTH 480
415 #define LCD_DISPLAY_HEIGHT 854
418 //#define CONFIG_FB_LCD_NT35516_MIPI
419 #define CONFIG_SYS_WHITE_ON_BLACK
420 #ifdef LCD_TEST_PATTERN
421 #define CONSOLE_COLOR_RED 0xf800
422 #define CONSOLE_COLOR_GREEN 0x07e0
423 #define CONSOLE_COLOR_YELLOW 0x07e0
424 #define CONSOLE_COLOR_BLUE 0x001f
425 #define CONSOLE_COLOR_MAGENTA 0x001f
426 #define CONSOLE_COLOR_CYAN 0x001f
430 #define CONFIG_SPRD_SYSDUMP
431 #include <asm/sizes.h>
434 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_1G - 1))) + SZ_1G - SZ_1M)
435 #elif defined(CONFIG_RAM512M)
436 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
437 #elif defined(CONFIG_RAM256M)
438 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_256M - 1))) + SZ_256M - SZ_1M)
439 //#elif defined(CONFIG_RAMxxxM)
440 //#define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_xxxM - 1))) + SZ_xxxM - SZ_1M) //xxx maybe 1024 etc
442 #error "CONFIG_RAMxxxM macro must be defined"
445 #define CALIBRATE_ENUM_MS 3000
446 #define CALIBRATE_IO_MS 2000
448 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
449 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
450 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
452 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
453 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
455 #define PHYS_OFFSET_ADDR 0x80000000
456 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
457 #define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
458 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*128M*/
459 #define WCDMA_CP_SDRAM_SIZE 0x1b00000 /*27M*/
460 #define WCN_CP_OFFSET_ADDR 0x0a800000 /*168M*/
461 #define WCN_CP_SDRAM_SIZE 0x201000 /*cp2size*/
463 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
464 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
465 #define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
466 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x899F0000*/
467 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x94EFF000*/
468 #define CALIBRATION_FLAG (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - 0x400)
469 #define CALIBRATION_FLAG_WCDMA CALIBRATION_FLAG
471 #define CONFIG_RAM_CONSOLE
473 #ifdef CONFIG_RAM_CONSOLE
474 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
475 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
477 //#define CALIBRATION_FLAG 0x89700000
479 #define CONFIG_CMD_SOUND 1
480 #define CONFIG_CMD_FOR_HTC 1
481 #define CONFIG_SOUND_CODEC_SPRD_V3 1
482 #define CONFIG_SOUND_DAI_VBC_R2P0 1
483 /* #define CONFIG_SPRD_AUDIO_DEBUG */
485 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
487 #define CONFIG_PBINT_7S_RESET_V0
489 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
491 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
492 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
494 #define USB_PHY_TUNE_VALUE 0x44073e33
496 /*control the CP need to boot*/
497 #define modem_cp0_enable 1
498 #define modem_cp1_enable 0
499 #define modem_cp2_enable 1
502 #endif /* __CONFIG_H */