2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 //#define CONFIG_OF_LIBFDT
25 //#ifdef CONFIG_OF_LIBFDT
26 //MACH_TYPE_SC8830=2014
28 #define DT_PLATFROM_ID 8830
29 #define DT_HARDWARE_ID 1
30 #define DT_SOC_VER 0x20000
32 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
33 #define CONFIG_FDL2_PRINT 0
34 #define BOOT_NATIVE_LINUX 1
35 #define BOOT_NATIVE_LINUX_MODEM 1
36 #define CONFIG_SILENT_CONSOLE
37 #define CONFIG_GPIOLIB 1
40 #define U_BOOT_SPRD_VER 1
41 /*#define SPRD_EVM_TAG_ON 1*/
42 #ifdef SPRD_EVM_TAG_ON
43 #define SPRD_EVM_ADDR_START 0x00026000
44 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
46 #define CONFIG_L2_OFF 1
50 #define CONFIG_YAFFS2 1
52 #define BOOT_PART "boot"
53 //#define BOOT_PART "kernel"
54 #define RECOVERY_PART "recovery"
55 #define UBIPAC_PART "ubipac"
58 * SPREADTRUM BIGPHONE board - SoC Configuration
64 #define CONFIG_SP7730GGAOPENPHONE
65 #define CONFIG_SP8830WCN
66 #define CONFIG_ADIE_SC2713S
68 #define CONFIG_SUPPORT_W
69 #define WDSP_ADR 0x88020000
70 #define WFIXNV_ADR 0x88240000
71 #define WRUNTIMENV_ADR 0x88280000
72 #define WMODEM_ADR 0x88300000
73 #define MODEM_ADR WMODEM_ADR
74 #define CONFIG_SUPPORT_WIFI
75 #define WCNMODEM_ADR 0x8a808000
76 #define WCNFIXNV_ADR 0x8a800000
77 #define WCNRUNTIMENV_ADR 0x8a820000
78 #define CP0_CODE_COPY_ADR 0x50000000
79 #define CP2_CODE_COPY_ADR 0x50003000
82 #define CONFIG_AUTODLOADER
84 #define CHIP_ENDIAN_LITTLE
85 #define _LITTLE_ENDIAN 1
87 #define CONFIG_RAM512M
90 #define CONFIG_EMMC_BOOT
93 #ifdef CONFIG_EMMC_BOOT
94 #define EMMC_SECTOR_SIZE 512
97 #define CONFIG_FS_EXT4
98 #define CONFIG_EXT4_WRITE
99 #define CONFIG_CMD_EXT4
100 #define CONFIG_CMD_EXT4_WRITE
102 //#define CONFIG_TIGER_MMC
103 #define CONFIG_UEFI_PARTITION
104 #define CONFIG_EFI_PARTITION
105 #define CONFIG_EXT4_SPARSE_DOWNLOAD
106 //#define CONFIG_EMMC_SPL
107 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
114 #define CONFIG_CMD_MMC
115 #ifdef CONFIG_CMD_MMC
116 #define CONFIG_CMD_FAT 1
117 #define CONFIG_FAT_WRITE 1
119 #define CONFIG_GENERIC_MMC 1
120 #define CONFIG_SDHCI 1
121 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
122 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
123 #define CONFIG_MMC_SDMA 1
124 #define CONFIG_MV_SDHCI 1
125 #define CONFIG_DOS_PARTITION 1
126 #define CONFIG_EFI_PARTITION 1
127 #define CONFIG_SYS_MMC_NUM 1
128 #define CONFIG_SYS_MMC_BASE {0x20600000}
129 #define CONFIG_SYS_SD_BASE 0x20300000
132 #define BB_DRAM_TYPE_256MB_32BIT
134 #define CONFIG_SYS_HZ 1000
135 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
137 //#define CONFIG_SYS_HUSH_PARSER
139 #ifdef CONFIG_SYS_HUSH_PARSER
140 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
143 #define FIXNV_SIZE (2*128 * 1024)
144 #define PRODUCTINFO_SIZE (16 * 1024)
145 #define WMODEM_SIZE (0x800000)
146 #define WDSP_SIZE (0x200000)
147 #define WCNMODEM_SIZE (0x100000)
148 #define VMJALUNA_SIZE (0x64000) /* 400K */
149 #define RUNTIMENV_SIZE (3*128 * 1024)
150 #define CONFIG_SPL_LOAD_LEN (0x6000)
152 #define PRODUCTINFO_ADR 0x80490000
154 /*#define CMDLINE_NEED_CONV */
156 #define WATCHDOG_LOAD_VALUE 0x4000
157 #define CONFIG_SYS_STACK_SIZE 0x400
158 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
160 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
162 /* NAND BOOT is the only boot method */
163 #define CONFIG_NAND_U_BOOT
164 #define DYNAMIC_CRC_TABLE
165 /* Start copying real U-boot from the second page */
166 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
167 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x90000
168 #define RAM_TYPPE_IS_SDRAM 0
169 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
171 /* Load U-Boot to this address */
172 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
173 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
174 #define CONFIG_SYS_SDRAM_BASE 0x80000000
175 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
177 #ifdef CONFIG_NAND_SPL
178 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
181 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
182 #define CONFIG_SYS_INIT_SP_ADDR \
183 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
185 #define CONFIG_SKIP_LOWLEVEL_INIT
188 #define CONFIG_HW_WATCHDOG
189 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
190 //#define CONFIG_DISPLAY_CPUINFO
192 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
193 #define CONFIG_SETUP_MEMORY_TAGS 1
194 #define CONFIG_INITRD_TAG 1
200 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
202 * Board has 2 32MB banks of DRAM but there is a bug when using
203 * both so only the first is configured
205 #define CONFIG_NR_DRAM_BANKS 1
207 #define PHYS_SDRAM_1 0x80000000
208 #define PHYS_SDRAM_1_SIZE 0x10000000
209 #if (CONFIG_NR_DRAM_BANKS == 2)
210 #define PHYS_SDRAM_2 0x90000000
211 #define PHYS_SDRAM_2_SIZE 0x10000000
214 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
215 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
216 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
221 #define CONFIG_SPRD_UART 1
222 #define CONFIG_SYS_SC8800X_UART1 1
223 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
224 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
225 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
226 #define CONFIG_SPRD_SPI
227 #define CONFIG_SPRD_I2C
228 #define CONFIG_SC8830_I2C
230 * Flash & Environment
232 /* No NOR flash present */
233 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
234 #define CONFIG_SYS_NO_FLASH 1
235 #define CONFIG_ENV_IS_NOWHERE
236 #define CONFIG_ENV_SIZE (128 * 1024)
238 #define CONFIG_ENV_IS_IN_NAND
239 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
240 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
244 #define CONFIG_CLK_PARA
246 #ifndef CONFIG_CLK_PARA
249 #define MAGIC_HEADER 0x5555AAAA
250 #define MAGIC_END 0xAAAA5555
251 #define CONFIG_PARA_VERSION 1
252 #define CLK_CA7_CORE ARM_CLK_1000M
253 #define CLK_CA7_AXI ARM_CLK_500M
254 #define CLK_CA7_DGB ARM_CLK_200M
255 #define CLK_CA7_AHB AHB_CLK_192M
256 #define CLK_CA7_APB APB_CLK_64M
257 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
258 #define CLK_AON_APB AON_APB_CLK_128M
259 #define DDR_FREQ 800000000
260 #define DCDC_ARM 1200
261 #define DCDC_CORE 1100
262 #define CONFIG_VOL_PARA
267 #define CONFIG_NAND_SC8830
268 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
269 #define CONFIG_SYS_MAX_NAND_DEVICE 1
270 #define CONFIG_SYS_NAND_BASE (0x20B00000)
271 //#define CONFIG_JFFS2_NAND
272 //#define CONFIG_SPRD_NAND_HWECC
273 #define CONFIG_SYS_NAND_HW_ECC
274 #define CONFIG_SYS_NAND_LARGEPAGE
275 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
277 #define CONFIG_SYS_64BIT_VSPRINTF
279 #define CONFIG_CMD_MTDPARTS
280 #define CONFIG_MTD_PARTITIONS
281 #define CONFIG_MTD_DEVICE
282 #define CONFIG_CMD_UBI
283 #define CONFIG_RBTREE
285 #define CONFIG_CMD_UBIFS
287 #ifdef CONFIG_CMD_UBIFS
288 #define CONFIG_FS_UBIFS
291 /* U-Boot general configuration */
292 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
293 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
294 /* Print buffer sz */
295 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
296 sizeof(CONFIG_SYS_PROMPT) + 16)
297 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
298 /* Boot Argument Buffer Size */
299 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
300 #define CONFIG_CMDLINE_EDITING
301 #define CONFIG_SYS_LONGHELP
303 /* support OS choose */
304 #undef CONFIG_BOOTM_NETBSD
305 #undef CONFIG_BOOTM_RTEMS
307 /* U-Boot commands */
308 #include <config_cmd_default.h>
309 #define CONFIG_CMD_NAND
310 #undef CONFIG_CMD_FPGA
311 #undef CONFIG_CMD_LOADS
312 #undef CONFIG_CMD_NET
313 #undef CONFIG_CMD_NFS
314 #undef CONFIG_CMD_SETGETDCR
316 #define CONFIG_ENV_OVERWRITE
318 #ifdef SPRD_EVM_TAG_ON
319 #define CONFIG_BOOTDELAY 0
321 #define CONFIG_BOOTDELAY 0
322 #define CONFIG_ZERO_BOOTDELAY_CHECK
325 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
326 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
328 #define xstr(s) str(s)
331 #ifdef CONFIG_RAM512M
332 #define MEM_INIT_PARA "mem=512M"
333 #elif defined(CONFIG_RAM256M)
334 #define MEM_INIT_PARA "mem=256M"
335 //#elif defined(CONFIG_RAMxxxM)
336 ////#define MEM_INIT_PARA "mem=xxxM" //xxx maybe 1024 etc
338 #error "CONFIG_RAMxxxM macro must be defined"
340 #define MTDIDS_DEFAULT "nand0=sprd-nand"
341 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),512k(2ndbl),256k(params),512k(vmjaluna),10m(modem),3840k(fixnv),3840k(backupfixnv),5120k(dsp),3840k(runtimenv),10m(boot),10m(recovery),250m(system),180m(userdata),20m(cache),256k(misc),1m(boot_logo),1m(fastboot_logo),3840k(productinfo),512k(kpanic)"
342 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),768k(2ndbl),512k(kpanic),-(ubipac)"
343 #define CONFIG_BOOTARGS MEM_INIT_PARA" loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
345 #define COPY_LINUX_KERNEL_SIZE (0x600000)
346 #define LINUX_INITRD_NAME "modem"
348 #define CONFIG_BOOTCOMMAND "cboot normal"
349 #define CONFIG_EXTRA_ENV_SETTINGS ""
351 #ifdef CONFIG_CMD_NET
352 #define CONFIG_IPADDR 192.168.10.2
353 #define CONFIG_SERVERIP 192.168.10.5
354 #define CONFIG_NETMASK 255.255.255.0
355 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
356 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
359 #define CONFIG_NET_MULTI
360 #define CONFIG_CMD_DNS
361 #define CONFIG_CMD_NFS
362 #define CONFIG_CMD_RARP
363 #define CONFIG_CMD_PING
364 /*#define CONFIG_CMD_SNTP */
367 #define CONFIG_USB_CORE_IP_293A
368 #define CONFIG_USB_GADGET_SC8800G
369 #define CONFIG_USB_DWC
370 #define CONFIG_USB_GADGET_DUALSPEED
371 //#define CONFIG_USB_ETHER
372 #define CONFIG_CMD_FASTBOOT
373 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
374 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
375 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
376 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
378 #define CONFIG_MODEM_CALIBERATE
382 #define CONFIG_DSIH_VERSION_1P21A
383 #define CONFIG_SPLASH_SCREEN
384 #define LCD_BPP LCD_COLOR16
385 //#define CONFIG_LCD_HVGA 1
386 //#define CONFIG_LCD_QVGA 1
387 #define CONFIG_LCD_QHD 1
388 //#define CONFIG_LCD_720P 1
389 //#define CONFIG_LCD_INFO
390 //#define LCD_TEST_PATTERN
391 //#define CONFIG_LCD_LOGO
392 //#define CONFIG_FB_LCD_S6D0139
393 #define CONFIG_FB_LCD_SSD2075_MIPI
394 #define CONFIG_FB_LCD_NT35516_MIPI
395 #define CONFIG_SYS_WHITE_ON_BLACK
396 #ifdef LCD_TEST_PATTERN
397 #define CONSOLE_COLOR_RED 0xf800
398 #define CONSOLE_COLOR_GREEN 0x07e0
399 #define CONSOLE_COLOR_YELLOW 0x07e0
400 #define CONSOLE_COLOR_BLUE 0x001f
401 #define CONSOLE_COLOR_MAGENTA 0x001f
402 #define CONSOLE_COLOR_CYAN 0x001f
406 #define CONFIG_SPRD_SYSDUMP
407 #include <asm/sizes.h>
409 #ifdef CONFIG_RAM512M
410 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
411 #elif defined(CONFIG_RAM256M)
412 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_256M - 1))) + SZ_256M - SZ_1M)
413 //#elif defined(CONFIG_RAMxxxM)
414 //#define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_xxxM - 1))) + SZ_xxxM - SZ_1M) //xxx maybe 1024 etc
416 #error "CONFIG_RAMxxxM macro must be defined"
419 #define CALIBRATE_ENUM_MS 3000
420 #define CALIBRATE_IO_MS 2000
422 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
423 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
424 #define LOW_BAT_VOL_CHG 3300 //3.3V charger connect
426 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
427 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
429 #define PHYS_OFFSET_ADDR 0x80000000
430 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
431 #define TD_CP_SDRAM_SIZE 0x1200000 /*18M*/
432 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*256M*/
433 #define WCDMA_CP_SDRAM_SIZE 0x1b00000 /*27M*/
434 #define WCN_CP_OFFSET_ADDR 0x0a800000 /*168M*/
435 #define WCN_CP_SDRAM_SIZE 0x201000 /*cp2size*/
437 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
438 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
439 #define SIPC_TD_APCP_START_ADDR (PHYS_OFFSET_ADDR + TD_CP_OFFSET_ADDR + TD_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x897FF000*/
440 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x899F0000*/
441 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE) /*0x94EFF000*/
442 #define CALIBRATION_FLAG (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - 0x400)
443 #define CALIBRATION_FLAG_WCDMA CALIBRATION_FLAG
445 #define CONFIG_RAM_CONSOLE
447 #ifdef CONFIG_RAM_CONSOLE
448 #define CONFIG_RAM_CONSOLE_SIZE 0x80000
449 #define CONFIG_RAM_CONSOLE_START (CONFIG_SYS_NAND_U_BOOT_START + 0x600000)
451 //#define CALIBRATION_FLAG 0x89700000
453 #define CONFIG_CMD_SOUND 1
454 #define CONFIG_CMD_FOR_HTC 1
455 #define CONFIG_SOUND_CODEC_SPRD_V3 1
456 #define CONFIG_SOUND_DAI_VBC_R2P0 1
457 /* #define CONFIG_SPRD_AUDIO_DEBUG */
459 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
461 #define CONFIG_PBINT_7S_RESET_V0
463 #define CONFIG_7S_RST_MODULE_EN 1 //0:disable module; 1:enable module
465 #define CONFIG_7S_RST_SW_MODE 1 //0:hw reset,1:arm reset,power keep on
466 #define CONFIG_7S_RST_SHORT_MODE 1 //0:long press then release key to trigger;1:press key some time to trigger
468 #define USB_PHY_TUNE_VALUE 0x44073e33
470 /*control the CP need to boot*/
471 #define modem_cp0_enable 1
472 #define modem_cp1_enable 0
473 #define modem_cp2_enable 1
475 #endif /* __CONFIG_H */