3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #undef USE_VGA_GRAPHICS
34 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
35 0x74000000 .... 0x740FFFFF -> CS#6
36 0x74100000 .... 0x741FFFFF -> CS#7
37 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
38 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
39 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
40 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
41 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
42 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
43 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
44 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
46 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
47 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
48 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
49 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
50 0xEED00000 .... 0xEED00003 -> PCI-Bus
51 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
52 0xEF40003F .... 0xEF5FFFFF -> reserved
53 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
54 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
55 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
56 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
57 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
58 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
61 #define CONFIG_SOLIDCARD3 1
63 #define CONFIG_405GP 1
65 #define CONFIG_BOARD_EARLY_INIT_F 1
68 * define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
69 * If undefed, IDE access uses a seperat emulation with higher access speed
70 * Consider to inform your Linux IDE driver about the different addresses!
71 * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes the CFG_CMD_IDE macro!
73 #define IDE_USES_ISA_EMULATION
75 /*-----------------------------------------------------------------------
77 *----------------------------------------------------------------------*/
78 #define CONFIG_SERIAL_MULTI
79 #undef CONFIG_SERIAL_SOFTWARE_FIFO
81 * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
82 * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
84 #if CONFIG_SERIAL_SOFTWARE_FIFO
85 #define CONFIG_POWER_DOWN
89 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
91 #define CONFIG_SYS_CLK_FREQ 33333333
94 * define CONFIG_BAUDRATE to the baudrate value you want to use as default
96 #define CONFIG_BAUDRATE 115200
97 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
99 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
100 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
102 #if 1 /* feel free to disable for development */
103 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
104 #define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n"
105 #define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */
109 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
110 * the CONFIG_BOOTDELAY delay to boot your machine
112 #define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
115 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
116 * set different values at the u-boot prompt
118 #ifdef USE_VGA_GRAPHICS
119 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
121 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
124 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
125 * This reserves memory bank #4 for this purpose
127 #undef CONFIG_ISP1161_PRESENT
129 #undef CONFIG_LOADS_ECHO /* no echo on for serial download */
130 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
132 #define CONFIG_NET_MULTI
133 /* #define CONFIG_EEPRO100_SROM_WRITE */
134 /* #define CONFIG_SHOW_MAC */
135 #define CONFIG_EEPRO100
136 #define CONFIG_MII 1 /* add 405GP MII PHY management */
137 #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
139 #define CONFIG_COMMANDS \
154 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
155 #include <cmd_confdefs.h>
157 #undef CONFIG_WATCHDOG /* watchdog disabled */
160 * Miscellaneous configurable options
162 #define CFG_LONGHELP 1 /* undef to save memory */
163 #define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
164 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
166 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
168 #define CFG_MAXARGS 16 /* max number of command args */
169 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
171 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
172 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
175 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
176 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
177 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
178 * The Linux BASE_BAUD define should match this configuration.
179 * baseBaud = cpuClock/(uartDivisor*16)
180 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
181 * set Linux BASE_BAUD to 403200.
183 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
184 * (see 405GP datasheet for descritpion)
186 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
187 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
188 #define CFG_BASE_BAUD 921600 /* internal clock */
190 /* The following table includes the supported baudrates */
191 #define CFG_BAUDRATE_TABLE \
192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
194 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
195 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
197 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
199 /*-----------------------------------------------------------------------
201 *-----------------------------------------------------------------------
203 #define CONFIG_HARD_I2C /* I2C with hardware support */
204 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
208 #define I2C_TRISTATE 0
210 #define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
211 #define CFG_I2C_SLAVE 0x7F /* mask valid bits */
213 #define CONFIG_RTC_DS1337
214 #define CFG_I2C_RTC_ADDR 0x68
216 /*-----------------------------------------------------------------------
218 *-----------------------------------------------------------------------
220 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
221 #define PCI_HOST_FORCE 1 /* configure as pci host */
222 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
224 #define CONFIG_PCI /* include pci support */
225 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
226 #define CONFIG_PCI_PNP /* do pci plug-and-play */
227 /* resource configuration */
229 /* If you want to see, whats connected to your PCI bus */
230 /* #define CONFIG_PCI_SCAN_SHOW */
232 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
233 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
234 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
235 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
236 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
237 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
238 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
239 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
241 /*-----------------------------------------------------------------------
242 * External peripheral base address
243 *-----------------------------------------------------------------------
245 #if !(CONFIG_COMMANDS & CFG_CMD_IDE)
247 #undef CONFIG_IDE_LED /* no led for ide supported */
248 #undef CONFIG_IDE_RESET /* no reset for ide supported */
250 /*-----------------------------------------------------------------------
252 *-----------------------------------------------------------------------
254 #else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
255 #define CONFIG_START_IDE 1 /* check, if use IDE */
257 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
258 #undef CONFIG_IDE_LED /* no led for ide supported */
259 #undef CONFIG_IDE_RESET /* no reset for ide supported */
262 #define CONFIG_DOS_PARTITION
263 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
265 #ifndef IDE_USES_ISA_EMULATION
267 /* New and faster access */
268 #define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
270 /* How many IDE busses are available */
271 #define CFG_IDE_MAXBUS 1
273 /* What IDE ports are available */
274 #define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
275 #undef CFG_ATA_IDE1_OFFSET /* second not available */
277 /* access to the data port is calculated:
278 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
279 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
281 /* access to the registers is calculated:
282 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
283 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
285 /* access to the alternate register is calculated:
286 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
287 #define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
289 #else /* IDE_USES_ISA_EMULATION */
291 #define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
293 /* How many IDE busses are available */
294 #define CFG_IDE_MAXBUS 1
296 /* What IDE ports are available */
297 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
298 #undef CFG_ATA_IDE1_OFFSET /* second not available */
300 /* access to the data port is calculated:
301 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
302 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
304 /* access to the registers is calculated:
305 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
306 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
308 /* access to the alternate register is calculated:
309 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
310 #define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
312 #endif /* IDE_USES_ISA_EMULATION */
314 #endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
317 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
318 #define CFG_IR_REG_BASE_ADDR 0xF0200000
319 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
322 /*-----------------------------------------------------------------------
323 * Start addresses for the final memory configuration
324 * (Set up by the startup code)
325 * Please note that CFG_SDRAM_BASE _must_ start at 0
327 * CFG_FLASH_BASE -> start address of internal flash
328 * CFG_MONITOR_BASE -> start of u-boot
330 #ifndef __ASSEMBLER__
331 extern unsigned long offsetOfBigFlash;
332 extern unsigned long offsetOfEnvironment;
335 #define CFG_SDRAM_BASE 0x00000000
336 #define CFG_FLASH_BASE 0xFFE00000
337 #define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
338 #define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
339 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
342 * For booting Linux, the board info and command line data
343 * have to be in the first 8 MiB of memory, since this is
344 * the maximum mapped by the Linux kernel during initialization.
346 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
347 /*-----------------------------------------------------------------------
348 * FLASH organization ## FIXME: lookup in datasheet
350 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
351 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
353 #define CFG_FLASH_CFI /* flash is CFI compat. */
354 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
355 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
356 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
357 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
358 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
360 #define CFG_ENV_IS_IN_FLASH 1
361 #if CFG_ENV_IS_IN_FLASH
362 #define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
363 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
364 #define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
366 /* let us changing anything in our environment */
367 #define CONFIG_ENV_OVERWRITE
372 #define CFG_MAX_NAND_DEVICE 1
373 #define NAND_MAX_CHIPS 1
374 #define CFG_NAND_BASE 0x77D00000
376 /*-----------------------------------------------------------------------
377 * Cache Configuration
379 * CFG_DCACHE_SIZE -> size of data cache:
382 * How to handle the difference in chache size?
383 * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
384 * (used in cpu/ppc4xx/start.S)
386 #define CFG_DCACHE_SIZE 16384
388 #define CFG_CACHELINE_SIZE 32
390 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
391 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
395 * Init Memory Controller:
399 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE
400 #define FLASH_BASE1_PRELIM 0
402 /*-----------------------------------------------------------------------
403 * Some informations about the internal SRAM (OCM=On Chip Memory)
405 * CFG_OCM_DATA_ADDR -> location
406 * CFG_OCM_DATA_SIZE -> size
409 #define CFG_TEMP_STACK_OCM 1
410 #define CFG_OCM_DATA_ADDR 0xF8000000
411 #define CFG_OCM_DATA_SIZE 0x1000
413 /*-----------------------------------------------------------------------
414 * Definitions for initial stack pointer and data area (in DPRAM):
415 * - we are using the internal 4k SRAM, so we don't need data cache mapping
416 * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
417 * - Stackpointer will be located to
418 * (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
419 * in cpu/ppc4xx/start.S
422 #undef CFG_INIT_DCACHE_CS
423 /* Where the internal SRAM starts */
424 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
425 /* Where the internal SRAM ends (only offset) */
426 #define CFG_INIT_RAM_END 0x0F00
430 CFG_INIT_RAM_ADDR ------> ------------ lower address
435 CFG_GBL_DATA_OFFSET ----> ------------
439 CFG_INIT_RAM_END ------> ------------ higher address
443 /* size in bytes reserved for initial data */
444 #define CFG_GBL_DATA_SIZE 64
445 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
446 /* Initial value of the stack pointern in internal SRAM */
447 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
450 * Internal Definitions
454 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
455 #define BOOTFLAG_WARM 0x02 /* Software reboot */
457 /* ################################################################################### */
458 /* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
459 /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
461 /* This chip select accesses the boot device */
462 /* It depends on boot select switch if this device is 16 or 8 bit */
488 #define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
489 #undef CONFIG_SPD_EEPROM
492 * Define this to get more information about system configuration
494 /* #define SC3_DEBUGOUT */
497 /***********************************************************************
498 * External peripheral base address
499 ***********************************************************************/
501 #define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
503 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
504 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
505 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
506 auf ISA- und PCI-Zyklen)
508 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
509 /*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
511 /************************************************************
513 ************************************************************/
515 #ifdef USE_VGA_GRAPHICS
516 #define CONFIG_VIDEO /* To enable video controller support */
517 #define CONFIG_VIDEO_CT69000
518 #define CONFIG_CFB_CONSOLE
519 /* #define CONFIG_VIDEO_LOGO */
520 #define CONFIG_VGA_AS_SINGLE_DEVICE
521 #define CONFIG_VIDEO_SW_CURSOR
522 /* #define CONFIG_VIDEO_HW_CURSOR */
523 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
525 #define VIDEO_HW_RECTFILL
526 #define VIDEO_HW_BITBLT
530 /************************************************************
532 ************************************************************/
533 #define CONFIG_SC3_VERSION "r1.4"
535 #define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
537 #endif /* __CONFIG_H */