Merge branch 'master' of git://git.denx.de/u-boot-sunxi
[platform/kernel/u-boot.git] / include / configs / socrates.h
1 /*
2  * (C) Copyright 2008
3  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4  *
5  * Wolfgang Denk <wd@denx.de>
6  * Copyright 2004 Freescale Semiconductor.
7  * (C) Copyright 2002,2003 Motorola,Inc.
8  * Xianghua Xiao <X.Xiao@motorola.com>
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 /*
14  * Socrates
15  */
16
17 #ifndef __CONFIG_H
18 #define __CONFIG_H
19
20 /* High Level Configuration Options */
21 #define CONFIG_SOCRATES         1
22
23 #define CONFIG_SYS_TEXT_BASE    0xfff80000
24
25 #define CONFIG_PCI_INDIRECT_BRIDGE
26
27 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
28
29 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
30 #define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_r      */
31
32 /*
33  * Only possible on E500 Version 2 or newer cores.
34  */
35 #define CONFIG_ENABLE_36BIT_PHYS        1
36
37 /*
38  * sysclk for MPC85xx
39  *
40  * Two valid values are:
41  *    33000000
42  *    66000000
43  *
44  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
45  * is likely the desired value here, so that is now the default.
46  * The board, however, can run at 66MHz.  In any event, this value
47  * must match the settings of some switches.  Details can be found
48  * in the README.mpc85xxads.
49  */
50
51 #ifndef CONFIG_SYS_CLK_FREQ
52 #define CONFIG_SYS_CLK_FREQ     66666666
53 #endif
54
55 /*
56  * These can be toggled for performance analysis, otherwise use default.
57  */
58 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
59 #define CONFIG_BTB                      /* toggle branch predition      */
60
61 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
62
63 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
64 #define CONFIG_SYS_MEMTEST_START        0x00400000
65 #define CONFIG_SYS_MEMTEST_END          0x00C00000
66
67 #define CONFIG_SYS_CCSRBAR              0xE0000000
68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
69
70 /* DDR Setup */
71 #undef CONFIG_FSL_DDR_INTERACTIVE
72 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
73 #define CONFIG_DDR_SPD
74
75 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
76 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
77
78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
80 #define CONFIG_VERY_BIG_RAM
81
82 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
83 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
84
85 /* I2C addresses of SPD EEPROMs */
86 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
87
88 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
89
90 /* Hardcoded values, to use instead of SPD */
91 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
92 #define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
93 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
94 #define CONFIG_SYS_DDR_TIMING_1         0x3935D322
95 #define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
96 #define CONFIG_SYS_DDR_MODE                     0x00480432
97 #define CONFIG_SYS_DDR_INTERVAL         0x030C0100
98 #define CONFIG_SYS_DDR_CONFIG_2         0x04400000
99 #define CONFIG_SYS_DDR_CONFIG                   0xC3008000
100 #define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
101 #define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
102
103 /*
104  * Flash on the LocalBus
105  */
106 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
107
108 #define CONFIG_SYS_FLASH0               0xFE000000
109 #define CONFIG_SYS_FLASH1               0xFC000000
110 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
111
112 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
113 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
114
115 #define CONFIG_SYS_BR0_PRELIM           0xfe001001      /* port size 16bit      */
116 #define CONFIG_SYS_OR0_PRELIM           0xfe000030      /* 32MB Flash           */
117 #define CONFIG_SYS_BR1_PRELIM           0xfc001001      /* port size 16bit      */
118 #define CONFIG_SYS_OR1_PRELIM           0xfe000030      /* 32MB Flash           */
119
120 #define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
121 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
122
123 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks      */
124 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
125 #undef  CONFIG_SYS_FLASH_CHECKSUM
126 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
128
129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
130
131 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
132 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
133 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
134 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
135
136 #define CONFIG_SYS_INIT_RAM_LOCK        1
137 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
138 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
139
140 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
142
143 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
144 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* Reserve 4 MB for malloc */
145
146 /* FPGA and NAND */
147 #define CONFIG_SYS_FPGA_BASE            0xc0000000
148 #define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
149 #define CONFIG_SYS_HMI_BASE             0xc0010000
150 #define CONFIG_SYS_BR3_PRELIM           0xc0001881      /* UPMA, 32-bit */
151 #define CONFIG_SYS_OR3_PRELIM           0xfff00000      /* 1 MB         */
152
153 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
154 #define CONFIG_SYS_MAX_NAND_DEVICE      1
155 #define CONFIG_CMD_NAND
156
157 /* LIME GDC */
158 #define CONFIG_SYS_LIME_BASE            0xc8000000
159 #define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
160 #define CONFIG_SYS_BR2_PRELIM           0xc80018a1      /* UPMB, 32-bit */
161 #define CONFIG_SYS_OR2_PRELIM           0xfc000000      /* 64 MB        */
162
163 #define CONFIG_VIDEO_MB862xx
164 #define CONFIG_VIDEO_MB862xx_ACCEL
165 #define CONFIG_VIDEO_LOGO
166 #define CONFIG_VIDEO_BMP_LOGO
167 #define VIDEO_FB_16BPP_PIXEL_SWAP
168 #define VIDEO_FB_16BPP_WORD_SWAP
169 #define CONFIG_SPLASH_SCREEN
170 #define CONFIG_VIDEO_BMP_GZIP
171 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
172
173 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
174 #define CONFIG_SYS_MB862xx_CCF          0x10000
175 /* SDRAM parameter */
176 #define CONFIG_SYS_MB862xx_MMR          0x4157BA63
177
178 /* Serial Port */
179
180 #define CONFIG_CONS_INDEX     1
181 #define CONFIG_SYS_NS16550_SERIAL
182 #define CONFIG_SYS_NS16550_REG_SIZE     1
183 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
184
185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
187
188 #define CONFIG_SYS_BAUDRATE_TABLE  \
189         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
190
191 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
192 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support */
193
194 /*
195  * I2C
196  */
197 #define CONFIG_SYS_I2C
198 #define CONFIG_SYS_I2C_FSL
199 #define CONFIG_SYS_FSL_I2C_SPEED        102124
200 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
201 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
202 #define CONFIG_SYS_FSL_I2C2_SPEED       102124
203 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
204 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
205
206 /* I2C RTC */
207 #define CONFIG_RTC_RX8025               /* Use Epson rx8025 rtc via i2c */
208 #define CONFIG_SYS_I2C_RTC_ADDR 0x32    /* at address 0x32              */
209
210 /* I2C W83782G HW-Monitoring IC */
211 #define CONFIG_SYS_I2C_W83782G_ADDR     0x28    /* W83782G address              */
212
213 /* I2C temp sensor */
214 /* Socrates uses Maxim's        DS75, which is compatible with LM75 */
215 #define CONFIG_DTT_LM75         1
216 #define CONFIG_DTT_SENSORS      {4}             /* Sensor addresses     */
217 #define CONFIG_SYS_DTT_MAX_TEMP 125
218 #define CONFIG_SYS_DTT_LOW_TEMP -55
219 #define CONFIG_SYS_DTT_HYSTERESIS       3
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
221
222 /*
223  * General PCI
224  * Memory space is mapped 1-1.
225  */
226 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
227
228 /* PCI is clocked by the external source at 33 MHz */
229 #define CONFIG_PCI_CLK_FREQ     33000000
230 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
231 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
232 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
233 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
234 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
235 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
236
237 #if defined(CONFIG_PCI)
238 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
239 #endif  /* CONFIG_PCI */
240
241 #define CONFIG_MII              1       /* MII PHY management */
242 #define CONFIG_TSEC1    1
243 #define CONFIG_TSEC1_NAME       "TSEC0"
244 #define CONFIG_TSEC3    1
245 #define CONFIG_TSEC3_NAME       "TSEC1"
246 #undef CONFIG_MPC85XX_FEC
247
248 #define TSEC1_PHY_ADDR          0
249 #define TSEC3_PHY_ADDR          1
250
251 #define TSEC1_PHYIDX            0
252 #define TSEC3_PHYIDX            0
253 #define TSEC1_FLAGS             TSEC_GIGABIT
254 #define TSEC3_FLAGS             TSEC_GIGABIT
255
256 /* Options are: TSEC[0,1] */
257 #define CONFIG_ETHPRIME         "TSEC0"
258 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
259
260 #define CONFIG_HAS_ETH0
261 #define CONFIG_HAS_ETH1
262
263 /*
264  * Environment
265  */
266 #define CONFIG_ENV_IS_IN_FLASH  1
267 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env     */
268 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
269 #define CONFIG_ENV_SIZE         0x4000
270 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
271 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
272
273 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
274 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
275
276 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
277
278 /*
279  * BOOTP options
280  */
281 #define CONFIG_BOOTP_BOOTFILESIZE
282 #define CONFIG_BOOTP_BOOTPATH
283 #define CONFIG_BOOTP_GATEWAY
284 #define CONFIG_BOOTP_HOSTNAME
285
286 /*
287  * Command line configuration.
288  */
289 #define CONFIG_CMD_DTT
290 #undef CONFIG_CMD_EEPROM
291 #define CONFIG_CMD_SDRAM
292 #define CONFIG_CMD_REGINFO
293
294 #if defined(CONFIG_PCI)
295     #define CONFIG_CMD_PCI
296 #endif
297
298 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
299
300 /*
301  * Miscellaneous configurable options
302  */
303 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
304 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
305
306 #if defined(CONFIG_CMD_KGDB)
307     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size      */
308 #else
309     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size      */
310 #endif
311
312 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size    */
313 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
314 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
315
316 /*
317  * For booting Linux, the board info and command line data
318  * have to be in the first 8 MB of memory, since this is
319  * the maximum mapped by the Linux kernel during initialization.
320  */
321 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
322
323 #if defined(CONFIG_CMD_KGDB)
324 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
325 #endif
326
327 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
328
329
330 #define CONFIG_PREBOOT  "echo;" \
331         "echo Welcome on the ABB Socrates Board;" \
332         "echo"
333
334 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
335
336 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
337         "netdev=eth0\0"                                                 \
338         "consdev=ttyS0\0"                                               \
339         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
340         "bootfile=/home/tftp/syscon3/uImage\0"                          \
341         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
342         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
343         "uboot_addr=FFFA0000\0"                                         \
344         "kernel_addr=FE000000\0"                                        \
345         "fdt_addr=FE1E0000\0"                                           \
346         "ramdisk_addr=FE200000\0"                                       \
347         "fdt_addr_r=B00000\0"                                           \
348         "kernel_addr_r=200000\0"                                        \
349         "ramdisk_addr_r=400000\0"                                       \
350         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
351         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
352         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
353                 "nfsroot=$serverip:$rootpath\0"                         \
354         "addcons=setenv bootargs $bootargs "                            \
355                 "console=$consdev,$baudrate\0"                          \
356         "addip=setenv bootargs $bootargs "                              \
357                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
358                 ":$hostname:$netdev:off panic=1\0"                      \
359         "boot_nor=run ramargs addcons;"                                 \
360                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
361         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
362                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
363                 "run nfsargs addip addcons;"                            \
364                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
365         "update_uboot=tftp 100000 ${uboot_file};"                       \
366                 "protect off fffa0000 ffffffff;"                        \
367                 "era fffa0000 ffffffff;"                                \
368                 "cp.b 100000 fffa0000 ${filesize};"                     \
369                 "setenv filesize;saveenv\0"                             \
370         "update_kernel=tftp 100000 ${bootfile};"                        \
371                 "era fe000000 fe1dffff;"                                \
372                 "cp.b 100000 fe000000 ${filesize};"                     \
373                 "setenv filesize;saveenv\0"                             \
374         "update_fdt=tftp 100000 ${fdt_file};"                           \
375                 "era fe1e0000 fe1fffff;"                                \
376                 "cp.b 100000 fe1e0000 ${filesize};"                     \
377                 "setenv filesize;saveenv\0"                             \
378         "update_initrd=tftp 100000 ${initrd_file};"                     \
379                 "era fe200000 fe9fffff;"                                \
380                 "cp.b 100000 fe200000 ${filesize};"                     \
381                 "setenv filesize;saveenv\0"                             \
382         "clean_data=era fea00000 fff5ffff\0"                            \
383         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
384         "load_usb=usb start;"                                           \
385                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
386         "boot_usb=run load_usb usbargs addcons;"                        \
387                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
388                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
389         ""
390 #define CONFIG_BOOTCOMMAND      "run boot_nor"
391
392 /* pass open firmware flat tree */
393
394 /* USB support */
395 #define CONFIG_USB_OHCI_NEW             1
396 #define CONFIG_PCI_OHCI                 1
397 #define CONFIG_PCI_OHCI_DEVNO           3 /* Number in PCI list */
398 #define CONFIG_PCI_EHCI_DEVNO           (CONFIG_PCI_OHCI_DEVNO / 2)
399 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
400 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
401 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
402
403 #endif  /* __CONFIG_H */