include/configs/socrates.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008
   4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5  *
   6  * Wolfgang Denk <wd@denx.de>
   7  * Copyright 2004 Freescale Semiconductor.
   8  * (C) Copyright 2002,2003 Motorola,Inc.
   9  * Xianghua Xiao <X.Xiao@motorola.com>
  10  */
  11
  12 /*
  13  * Socrates
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SOCRATES         1
  21
  22 /*
  23  * Only possible on E500 Version 2 or newer cores.
  24  */
  25 #define CONFIG_ENABLE_36BIT_PHYS        1
  26
  27 /*
  28  * sysclk for MPC85xx
  29  *
  30  * Two valid values are:
  31  *    33000000
  32  *    66000000
  33  *
  34  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  35  * is likely the desired value here, so that is now the default.
  36  * The board, however, can run at 66MHz.  In any event, this value
  37  * must match the settings of some switches.  Details can be found
  38  * in the README.mpc85xxads.
  39  */
  40
  41 /*
  42  * These can be toggled for performance analysis, otherwise use default.
  43  */
  44 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  45
  46 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
  47
  48 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
  49
  50 #define CONFIG_SYS_CCSRBAR              0xE0000000
  51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  52
  53 /* DDR Setup */
  54 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  55
  56 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  57
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  59 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  60 #define CONFIG_VERY_BIG_RAM
  61
  62 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  63 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  64
  65 /* I2C addresses of SPD EEPROMs */
  66 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
  67
  68
  69 /* Hardcoded values, to use instead of SPD */
  70 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  71 #define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
  72 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
  73 #define CONFIG_SYS_DDR_TIMING_1         0x3935D322
  74 #define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
  75 #define CONFIG_SYS_DDR_MODE                     0x00480432
  76 #define CONFIG_SYS_DDR_INTERVAL         0x030C0100
  77 #define CONFIG_SYS_DDR_CONFIG_2         0x04400000
  78 #define CONFIG_SYS_DDR_CONFIG                   0xC3008000
  79 #define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
  80 #define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
  81
  82 /*
  83  * Flash on the LocalBus
  84  */
  85 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
  86
  87 #define CONFIG_SYS_FLASH_QUIET_TEST
  88 #define CONFIG_SYS_FLASH0               0xFE000000
  89 #define CONFIG_SYS_FLASH1               0xFC000000
  90 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  91
  92 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
  93 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
  94
  95 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
  96 #undef  CONFIG_SYS_FLASH_CHECKSUM
  97 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
  98 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
  99
 100 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 101
 102 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
 103 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
 104 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 105 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
 106
 107 #define CONFIG_SYS_INIT_RAM_LOCK        1
 108 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
 109 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
 110
 111 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 113
 114 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
 115
 116 /* FPGA and NAND */
 117 #define CONFIG_SYS_FPGA_BASE            0xc0000000
 118 #define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
 119 #define CONFIG_SYS_HMI_BASE             0xc0010000
 120
 121 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
 122 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 123
 124 /* LIME GDC */
 125 #define CONFIG_SYS_LIME_BASE            0xc8000000
 126 #define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
 127
 128 #define CONFIG_SYS_SPD_BUS_NUM 0
 129
 130 /*
 131  * General PCI
 132  * Memory space is mapped 1-1.
 133  */
 134
 135 /* PCI is clocked by the external source at 33 MHz */
 136 #define CONFIG_PCI_CLK_FREQ     33000000
 137 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 138 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 139 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 140 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
 141 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 142 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
 143
 144 #define CONFIG_TSEC1    1
 145 #define CONFIG_TSEC1_NAME       "TSEC0"
 146 #define CONFIG_TSEC3    1
 147 #define CONFIG_TSEC3_NAME       "TSEC1"
 148 #undef CONFIG_MPC85XX_FEC
 149
 150 #define TSEC1_PHY_ADDR          0
 151 #define TSEC3_PHY_ADDR          1
 152
 153 #define TSEC1_PHYIDX            0
 154 #define TSEC3_PHYIDX            0
 155 #define TSEC1_FLAGS             TSEC_GIGABIT
 156 #define TSEC3_FLAGS             TSEC_GIGABIT
 157
 158 /* Options are: TSEC[0,1] */
 159 #define CONFIG_ETHPRIME         "TSEC0"
 160
 161 #define CONFIG_HAS_ETH0
 162 #define CONFIG_HAS_ETH1
 163
 164 /*
 165  * Environment
 166  */
 167
 168 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 169 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 170
 171 /*
 172  * Miscellaneous configurable options
 173  */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 181
 182
 183 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 184         "netdev=eth0\0"                                                 \
 185         "consdev=ttyS0\0"                                               \
 186         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
 187         "bootfile=/home/tftp/syscon3/uImage\0"                          \
 188         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
 189         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
 190         "uboot_addr=FFF60000\0"                                         \
 191         "kernel_addr=FE000000\0"                                        \
 192         "fdt_addr=FE1E0000\0"                                           \
 193         "ramdisk_addr=FE200000\0"                                       \
 194         "fdt_addr_r=B00000\0"                                           \
 195         "kernel_addr_r=200000\0"                                        \
 196         "ramdisk_addr_r=400000\0"                                       \
 197         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
 198         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 199         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 200                 "nfsroot=$serverip:$rootpath\0"                         \
 201         "addcons=setenv bootargs $bootargs "                            \
 202                 "console=$consdev,$baudrate\0"                          \
 203         "addip=setenv bootargs $bootargs "                              \
 204                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 205                 ":$hostname:$netdev:off panic=1\0"                      \
 206         "boot_nor=run ramargs addcons;"                                 \
 207                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 208         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 209                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 210                 "run nfsargs addip addcons;"                            \
 211                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 212         "update_uboot=tftp 100000 ${uboot_file};"                       \
 213                 "protect off fff60000 ffffffff;"                        \
 214                 "era fff60000 ffffffff;"                                \
 215                 "cp.b 100000 fff60000 ${filesize};"                     \
 216                 "setenv filesize;saveenv\0"                             \
 217         "update_kernel=tftp 100000 ${bootfile};"                        \
 218                 "era fe000000 fe1dffff;"                                \
 219                 "cp.b 100000 fe000000 ${filesize};"                     \
 220                 "setenv filesize;saveenv\0"                             \
 221         "update_fdt=tftp 100000 ${fdt_file};"                           \
 222                 "era fe1e0000 fe1fffff;"                                \
 223                 "cp.b 100000 fe1e0000 ${filesize};"                     \
 224                 "setenv filesize;saveenv\0"                             \
 225         "update_initrd=tftp 100000 ${initrd_file};"                     \
 226                 "era fe200000 fe9fffff;"                                \
 227                 "cp.b 100000 fe200000 ${filesize};"                     \
 228                 "setenv filesize;saveenv\0"                             \
 229         "clean_data=era fea00000 fff5ffff\0"                            \
 230         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
 231         "load_usb=usb start;"                                           \
 232                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
 233         "boot_usb=run load_usb usbargs addcons;"                        \
 234                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
 235                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 236         ""
 237
 238 /* pass open firmware flat tree */
 239
 240 /* USB support */
 241 #define CONFIG_USB_OHCI_NEW             1
 242 #define CONFIG_PCI_OHCI                 1
 243 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 244 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 245 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 246
 247 #endif  /* __CONFIG_H */