include/configs/socrates.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008
   4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5  *
   6  * Wolfgang Denk <wd@denx.de>
   7  * Copyright 2004 Freescale Semiconductor.
   8  * (C) Copyright 2002,2003 Motorola,Inc.
   9  * Xianghua Xiao <X.Xiao@motorola.com>
  10  */
  11
  12 /*
  13  * Socrates
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SOCRATES         1
  21
  22 /*
  23  * Only possible on E500 Version 2 or newer cores.
  24  */
  25 #define CONFIG_ENABLE_36BIT_PHYS        1
  26
  27 /*
  28  * sysclk for MPC85xx
  29  *
  30  * Two valid values are:
  31  *    33000000
  32  *    66000000
  33  *
  34  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  35  * is likely the desired value here, so that is now the default.
  36  * The board, however, can run at 66MHz.  In any event, this value
  37  * must match the settings of some switches.  Details can be found
  38  * in the README.mpc85xxads.
  39  */
  40
  41 /*
  42  * These can be toggled for performance analysis, otherwise use default.
  43  */
  44 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  45 #define CONFIG_BTB                      /* toggle branch predition      */
  46
  47 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
  48
  49 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
  50
  51 #define CONFIG_SYS_CCSRBAR              0xE0000000
  52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  53
  54 /* DDR Setup */
  55 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  56
  57 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  58
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  61 #define CONFIG_VERY_BIG_RAM
  62
  63 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  64 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  65
  66 /* I2C addresses of SPD EEPROMs */
  67 #define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
  68
  69
  70 /* Hardcoded values, to use instead of SPD */
  71 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  72 #define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
  73 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
  74 #define CONFIG_SYS_DDR_TIMING_1         0x3935D322
  75 #define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
  76 #define CONFIG_SYS_DDR_MODE                     0x00480432
  77 #define CONFIG_SYS_DDR_INTERVAL         0x030C0100
  78 #define CONFIG_SYS_DDR_CONFIG_2         0x04400000
  79 #define CONFIG_SYS_DDR_CONFIG                   0xC3008000
  80 #define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
  81 #define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
  82
  83 /*
  84  * Flash on the LocalBus
  85  */
  86 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
  87
  88 #define CONFIG_SYS_FLASH_QUIET_TEST
  89 #define CONFIG_SYS_FLASH0               0xFE000000
  90 #define CONFIG_SYS_FLASH1               0xFC000000
  91 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  92
  93 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
  94 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
  95
  96 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks      */
  97 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
  98 #undef  CONFIG_SYS_FLASH_CHECKSUM
  99 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 100 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 101
 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 103
 104 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
 105 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
 106 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 107 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
 108
 109 #define CONFIG_SYS_INIT_RAM_LOCK        1
 110 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
 111 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
 112
 113 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 114 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 115
 116 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
 117
 118 /* FPGA and NAND */
 119 #define CONFIG_SYS_FPGA_BASE            0xc0000000
 120 #define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
 121 #define CONFIG_SYS_HMI_BASE             0xc0010000
 122
 123 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
 124 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 125
 126 /* LIME GDC */
 127 #define CONFIG_SYS_LIME_BASE            0xc8000000
 128 #define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
 129
 130 #define CONFIG_SYS_SPD_BUS_NUM 0
 131
 132 /*
 133  * General PCI
 134  * Memory space is mapped 1-1.
 135  */
 136
 137 /* PCI is clocked by the external source at 33 MHz */
 138 #define CONFIG_PCI_CLK_FREQ     33000000
 139 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 140 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 141 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 142 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
 143 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 144 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
 145
 146 #define CONFIG_TSEC1    1
 147 #define CONFIG_TSEC1_NAME       "TSEC0"
 148 #define CONFIG_TSEC3    1
 149 #define CONFIG_TSEC3_NAME       "TSEC1"
 150 #undef CONFIG_MPC85XX_FEC
 151
 152 #define TSEC1_PHY_ADDR          0
 153 #define TSEC3_PHY_ADDR          1
 154
 155 #define TSEC1_PHYIDX            0
 156 #define TSEC3_PHYIDX            0
 157 #define TSEC1_FLAGS             TSEC_GIGABIT
 158 #define TSEC3_FLAGS             TSEC_GIGABIT
 159
 160 /* Options are: TSEC[0,1] */
 161 #define CONFIG_ETHPRIME         "TSEC0"
 162
 163 #define CONFIG_HAS_ETH0
 164 #define CONFIG_HAS_ETH1
 165
 166 /*
 167  * Environment
 168  */
 169
 170 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 171 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 172
 173 /*
 174  * BOOTP options
 175  */
 176 #define CONFIG_BOOTP_BOOTFILESIZE
 177
 178 /*
 179  * Miscellaneous configurable options
 180  */
 181
 182 /*
 183  * For booting Linux, the board info and command line data
 184  * have to be in the first 8 MB of memory, since this is
 185  * the maximum mapped by the Linux kernel during initialization.
 186  */
 187 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 188
 189
 190 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 191         "netdev=eth0\0"                                                 \
 192         "consdev=ttyS0\0"                                               \
 193         "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
 194         "bootfile=/home/tftp/syscon3/uImage\0"                          \
 195         "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
 196         "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
 197         "uboot_addr=FFF60000\0"                                         \
 198         "kernel_addr=FE000000\0"                                        \
 199         "fdt_addr=FE1E0000\0"                                           \
 200         "ramdisk_addr=FE200000\0"                                       \
 201         "fdt_addr_r=B00000\0"                                           \
 202         "kernel_addr_r=200000\0"                                        \
 203         "ramdisk_addr_r=400000\0"                                       \
 204         "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
 205         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 206         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 207                 "nfsroot=$serverip:$rootpath\0"                         \
 208         "addcons=setenv bootargs $bootargs "                            \
 209                 "console=$consdev,$baudrate\0"                          \
 210         "addip=setenv bootargs $bootargs "                              \
 211                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 212                 ":$hostname:$netdev:off panic=1\0"                      \
 213         "boot_nor=run ramargs addcons;"                                 \
 214                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 215         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 216                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 217                 "run nfsargs addip addcons;"                            \
 218                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 219         "update_uboot=tftp 100000 ${uboot_file};"                       \
 220                 "protect off fff60000 ffffffff;"                        \
 221                 "era fff60000 ffffffff;"                                \
 222                 "cp.b 100000 fff60000 ${filesize};"                     \
 223                 "setenv filesize;saveenv\0"                             \
 224         "update_kernel=tftp 100000 ${bootfile};"                        \
 225                 "era fe000000 fe1dffff;"                                \
 226                 "cp.b 100000 fe000000 ${filesize};"                     \
 227                 "setenv filesize;saveenv\0"                             \
 228         "update_fdt=tftp 100000 ${fdt_file};"                           \
 229                 "era fe1e0000 fe1fffff;"                                \
 230                 "cp.b 100000 fe1e0000 ${filesize};"                     \
 231                 "setenv filesize;saveenv\0"                             \
 232         "update_initrd=tftp 100000 ${initrd_file};"                     \
 233                 "era fe200000 fe9fffff;"                                \
 234                 "cp.b 100000 fe200000 ${filesize};"                     \
 235                 "setenv filesize;saveenv\0"                             \
 236         "clean_data=era fea00000 fff5ffff\0"                            \
 237         "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
 238         "load_usb=usb start;"                                           \
 239                 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
 240         "boot_usb=run load_usb usbargs addcons;"                        \
 241                 "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
 242                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 243         ""
 244
 245 /* pass open firmware flat tree */
 246
 247 /* USB support */
 248 #define CONFIG_USB_OHCI_NEW             1
 249 #define CONFIG_PCI_OHCI                 1
 250 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 251 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 252 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 253
 254 #endif  /* __CONFIG_H */