1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
6 * Wolfgang Denk <wd@denx.de>
7 * Copyright 2004 Freescale Semiconductor.
8 * (C) Copyright 2002,2003 Motorola,Inc.
9 * Xianghua Xiao <X.Xiao@motorola.com>
19 /* High Level Configuration Options */
20 #define CONFIG_SOCRATES 1
23 * Only possible on E500 Version 2 or newer cores.
29 * Two valid values are:
33 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
34 * is likely the desired value here, so that is now the default.
35 * The board, however, can run at 66MHz. In any event, this value
36 * must match the settings of some switches. Details can be found
37 * in the README.mpc85xxads.
41 * These can be toggled for performance analysis, otherwise use default.
43 #define CONFIG_L2_CACHE /* toggle L2 cache */
45 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
47 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
49 #define CONFIG_SYS_CCSRBAR 0xE0000000
50 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
53 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
58 #define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
59 #define CONFIG_VERY_BIG_RAM
61 /* I2C addresses of SPD EEPROMs */
62 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
65 /* Hardcoded values, to use instead of SPD */
66 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
67 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
68 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
69 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322
70 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
71 #define CONFIG_SYS_DDR_MODE 0x00480432
72 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100
73 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000
74 #define CONFIG_SYS_DDR_CONFIG 0xC3008000
75 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
76 #define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
79 * Flash on the LocalBus
81 #define CONFIG_SYS_FLASH0 0xFE000000
82 #define CONFIG_SYS_FLASH1 0xFC000000
83 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
85 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
86 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
88 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
89 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
90 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
91 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
93 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
94 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
96 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
99 #define CONFIG_SYS_FPGA_BASE 0xc0000000
100 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
102 #define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
105 #define CONFIG_SYS_LIME_BASE 0xc8000000
109 * Memory space is mapped 1-1.
112 #define CFG_SYS_PCI1_MEM_PHYS 0x80000000
113 #define CFG_SYS_PCI1_IO_PHYS 0xE2000000
115 #define CONFIG_TSEC1 1
116 #define CONFIG_TSEC1_NAME "TSEC0"
117 #define CONFIG_TSEC3 1
118 #define CONFIG_TSEC3_NAME "TSEC1"
119 #undef CONFIG_MPC85XX_FEC
121 #define TSEC1_PHY_ADDR 0
122 #define TSEC3_PHY_ADDR 1
124 #define TSEC1_PHYIDX 0
125 #define TSEC3_PHYIDX 0
126 #define TSEC1_FLAGS TSEC_GIGABIT
127 #define TSEC3_FLAGS TSEC_GIGABIT
129 /* Options are: TSEC[0,1] */
132 * Miscellaneous configurable options
136 * For booting Linux, the board info and command line data
137 * have to be in the first 8 MB of memory, since this is
138 * the maximum mapped by the Linux kernel during initialization.
140 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
143 #define CONFIG_EXTRA_ENV_SETTINGS \
146 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
147 "bootfile=/home/tftp/syscon3/uImage\0" \
148 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
149 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
150 "uboot_addr=FFF60000\0" \
151 "kernel_addr=FE000000\0" \
152 "fdt_addr=FE1E0000\0" \
153 "ramdisk_addr=FE200000\0" \
154 "fdt_addr_r=B00000\0" \
155 "kernel_addr_r=200000\0" \
156 "ramdisk_addr_r=400000\0" \
157 "rootpath=/opt/eldk/ppc_85xxDP\0" \
158 "ramargs=setenv bootargs root=/dev/ram rw\0" \
159 "nfsargs=setenv bootargs root=/dev/nfs rw " \
160 "nfsroot=$serverip:$rootpath\0" \
161 "addcons=setenv bootargs $bootargs " \
162 "console=$consdev,$baudrate\0" \
163 "addip=setenv bootargs $bootargs " \
164 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
165 ":$hostname:$netdev:off panic=1\0" \
166 "boot_nor=run ramargs addcons;" \
167 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
168 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
169 "tftp ${fdt_addr_r} ${fdt_file}; " \
170 "run nfsargs addip addcons;" \
171 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
172 "update_uboot=tftp 100000 ${uboot_file};" \
173 "protect off fff60000 ffffffff;" \
174 "era fff60000 ffffffff;" \
175 "cp.b 100000 fff60000 ${filesize};" \
176 "setenv filesize;saveenv\0" \
177 "update_kernel=tftp 100000 ${bootfile};" \
178 "era fe000000 fe1dffff;" \
179 "cp.b 100000 fe000000 ${filesize};" \
180 "setenv filesize;saveenv\0" \
181 "update_fdt=tftp 100000 ${fdt_file};" \
182 "era fe1e0000 fe1fffff;" \
183 "cp.b 100000 fe1e0000 ${filesize};" \
184 "setenv filesize;saveenv\0" \
185 "update_initrd=tftp 100000 ${initrd_file};" \
186 "era fe200000 fe9fffff;" \
187 "cp.b 100000 fe200000 ${filesize};" \
188 "setenv filesize;saveenv\0" \
189 "clean_data=era fea00000 fff5ffff\0" \
190 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
191 "load_usb=usb start;" \
192 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
193 "boot_usb=run load_usb usbargs addcons;" \
194 "bootm ${kernel_addr_r} - ${fdt_addr};" \
195 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
198 /* pass open firmware flat tree */
200 #endif /* __CONFIG_H */