1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
5 #ifndef __CONFIG_SOCFPGA_SR1500_H__
6 #define __CONFIG_SOCFPGA_SR1500_H__
8 #include <asm/arch/base_addr_ac5.h>
10 /* Memory configurations */
11 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
14 #define CONFIG_SYS_LOAD_ADDR 0x01000000
16 /* Ethernet on SoC (EMAC) */
17 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
18 /* The PHY is autodetected, so no MII PHY address is needed here */
19 #define PHY_ANEG_TIMEOUT 8000
21 /* Enable SPI NOR flash reset, needed for SPI booting */
22 #define CONFIG_SPI_N25Q256A_RESET
27 #define CONFIG_SYS_BOOTCOUNT_BE
29 /* Environment setting for SPI flash */
31 /* The rest of the configuration is shared */
32 #include <configs/socfpga_common.h>
34 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */