2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_SR1500_H__
7 #define __CONFIG_SOCFPGA_SR1500_H__
9 #include <asm/arch/base_addr_ac5.h>
11 #define CONFIG_BOARD_EARLY_INIT_F
13 #define CONFIG_SYS_NO_FLASH
14 #define CONFIG_DOS_PARTITION
15 #define CONFIG_FAT_WRITE
17 #define CONFIG_HW_WATCHDOG
20 #define CONFIG_CMD_ASKENV
21 #define CONFIG_CMD_BOOTZ
22 #define CONFIG_CMD_CACHE
23 #define CONFIG_CMD_DHCP
24 #define CONFIG_CMD_EXT4
25 #define CONFIG_CMD_EXT4_WRITE
26 #define CONFIG_CMD_FAT
27 #define CONFIG_CMD_FS_GENERIC
28 #define CONFIG_CMD_GPIO
29 #define CONFIG_CMD_GREPENV
30 #define CONFIG_CMD_MEMTEST
31 #define CONFIG_CMD_MII
32 #define CONFIG_CMD_MMC
33 #define CONFIG_CMD_PING
35 #define CONFIG_CMD_SPI
36 #define CONFIG_CMD_TIME
38 /* Memory configurations */
39 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
42 #define CONFIG_BOOTDELAY 3
43 #define CONFIG_BOOTFILE "uImage"
44 #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
45 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
46 #define CONFIG_LOADADDR 0x01000000
47 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
48 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
50 /* Ethernet on SoC (EMAC) */
51 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
52 /* The PHY is autodetected, so no MII PHY address is needed here */
53 #define CONFIG_PHY_MARVELL
54 #define PHY_ANEG_TIMEOUT 8000
56 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
59 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
60 "bootm ${loadaddr} - ${fdt_addr}\0" \
61 "bootimage=zImage\0" \
63 "fdtimage=socfpga.dtb\0" \
64 "fsloadcmd=ext2load\0" \
65 "bootm ${loadaddr} - ${fdt_addr}\0" \
66 "mmcroot=/dev/mmcblk0p2\0" \
67 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
68 " root=${mmcroot} rw rootwait;" \
69 "bootz ${loadaddr} - ${fdt_addr}\0" \
70 "mmcload=mmc rescan;" \
71 "load mmc 0:1 ${loadaddr} ${bootimage};" \
72 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
73 "qspiload=sf probe && mtdparts default && run ubiload\0" \
74 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
75 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
76 "bootz ${loadaddr} - ${fdt_addr}\0" \
77 "ubiload=ubi part UBI && ubifsmount ubi0 && " \
78 "ubifsload ${loadaddr} /boot/${bootimage} && " \
79 "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
82 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 /* Enable SPI NOR flash reset, needed for SPI booting */
85 #define CONFIG_SPI_N25Q256A_RESET
90 #define CONFIG_BOOTCOUNT_LIMIT
91 /* last 2 lwords in OCRAM */
92 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
93 #define CONFIG_SYS_BOOTCOUNT_BE
95 /* Environment setting for SPI flash */
96 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
97 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
98 #define CONFIG_ENV_SIZE (16 * 1024)
99 #define CONFIG_ENV_OFFSET 0x000e0000
100 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
101 #define CONFIG_ENV_SPI_BUS 0
102 #define CONFIG_ENV_SPI_CS 0
103 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
104 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
105 #define CONFIG_SF_DEFAULT_SPEED 100000000
108 * The QSPI NOR flash layout on SR1500:
110 * 0000.0000 - 0003.ffff: SPL (4 times)
111 * 0004.0000 - 000d.ffff: U-Boot
112 * 000e.0000 - 000e.ffff: env1
113 * 000f.0000 - 000f.ffff: env2
116 /* The rest of the configuration is shared */
117 #include <configs/socfpga_common.h>
119 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */