1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
10 #include <asm/arch/base_addr_soc64.h>
11 #include <asm/arch/handoff_soc64.h>
12 #include <linux/stringify.h>
15 * U-Boot general configurations
17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
18 #define CPU_RELEASE_ADDR 0xFFD12210
21 * U-Boot console configurations
23 #define CONFIG_SYS_CBSIZE 2048
24 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
26 /* Extend size of kernel image for uncompression */
27 #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
30 * U-Boot run time memory configurations
32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
33 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
36 + CONFIG_SYS_INIT_RAM_SIZE \
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
42 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
45 * U-Boot environment configurations
51 #ifdef CONFIG_CADENCE_QSPI
52 /* Enable it if you want to use dual-stacked mode */
53 /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
55 /* Flash device info */
57 #ifndef CONFIG_SPL_BUILD
58 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
59 #endif /* CONFIG_SPL_BUILD */
61 #endif /* CONFIG_CADENCE_QSPI */
64 * Environment variable
66 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
68 "bootfile=" CONFIG_BOOTFILE "\0" \
69 "fdt_addr=8000000\0" \
70 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
71 "mmcroot=/dev/mmcblk0p2\0" \
72 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
73 " root=${mmcroot} rw rootwait;" \
74 "booti ${loadaddr} - ${fdt_addr}\0" \
75 "mmcload=mmc rescan;" \
76 "load mmc 0:1 ${loadaddr} ${bootfile};" \
77 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
78 "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
79 " root=${mmcroot} rw rootwait;" \
80 "bootm ${loadaddr}\0" \
81 "mmcfitload=mmc rescan;" \
82 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
83 "linux_qspi_enable=if sf probe; then " \
84 "echo Enabling QSPI at Linux DTB...;" \
85 "fdt addr ${fdt_addr}; fdt resize;" \
86 "fdt set /soc/spi@ff8d2000 status okay;" \
87 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
88 " ${qspi_clock}; fi; \0" \
89 "scriptaddr=0x02100000\0" \
90 "scriptfile=u-boot.scr\0" \
91 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
92 "then source ${scriptaddr}; fi\0" \
93 "socfpga_legacy_reset_compat=1\0"
96 * External memory configurations
98 #define PHYS_SDRAM_1 0x0
99 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
100 #define CONFIG_SYS_SDRAM_BASE 0
103 * Serial / UART configurations
105 #define CONFIG_SYS_NS16550_CLK 100000000
106 #define CONFIG_SYS_NS16550_MEM32
109 * SDMMC configurations
111 #ifdef CONFIG_CMD_MMC
112 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
115 * Flash configurations
118 /* Ethernet on SoC (EMAC) */
119 #if defined(CONFIG_CMD_NET)
120 #define CONFIG_DW_ALTDESCRIPTOR
121 #endif /* CONFIG_CMD_NET */
126 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
127 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
129 unsigned int cm_get_l4_sys_free_clk_hz(void);
130 #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
133 #define CONFIG_DW_WDT_CLOCK_KHZ 100000
140 * 0xFFE0_0000 ...... Start of OCRAM
143 * 0xFFEx_xxxx ...... Top of stack (grows down)
144 * 0xFFEy_yyyy ...... Global Data
145 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
146 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
147 * 0xFFE3_FFFF ...... End of OCRAM
150 * 0x0000_0000 ...... Start of SDRAM_1
151 * unused / empty space for image loading
152 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
153 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
154 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
157 #define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex"
158 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
159 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
160 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
161 #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
162 - CONFIG_SPL_BSS_MAX_SIZE)
163 #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
164 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
165 - CONFIG_SYS_SPL_MALLOC_SIZE)
167 /* SPL SDMMC boot support */
168 #ifdef CONFIG_SPL_LOAD_FIT
169 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
171 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
174 #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */