include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23 #define CONFIG_SYS_CBSIZE               2048
  24 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  25                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  26 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  27
  28 /* Extend size of kernel image for uncompression */
  29 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  30
  31 /*
  32  * U-Boot run time memory configurations
  33  */
  34 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  35 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  36 #ifdef CONFIG_SPL_BUILD
  37 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  38                                         + CONFIG_SYS_INIT_RAM_SIZE \
  39                                         - SOC64_HANDOFF_SIZE)
  40 #else
  41 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  42                                         + 0x100000)
  43 #endif
  44 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  45
  46 /*
  47  * U-Boot environment configurations
  48  */
  49
  50 /*
  51  * QSPI support
  52  */
  53  #ifdef CONFIG_CADENCE_QSPI
  54 /* Enable it if you want to use dual-stacked mode */
  55 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  56
  57 /* Flash device info */
  58
  59 #ifndef CONFIG_SPL_BUILD
  60 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  61 #endif /* CONFIG_SPL_BUILD */
  62
  63 #endif /* CONFIG_CADENCE_QSPI */
  64
  65 /*
  66  * Environment variable
  67  */
  68 #define CONFIG_EXTRA_ENV_SETTINGS \
  69         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  70         "bootfile=" CONFIG_BOOTFILE "\0" \
  71         "fdt_addr=8000000\0" \
  72         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  73         "mmcroot=/dev/mmcblk0p2\0" \
  74         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  75                 " root=${mmcroot} rw rootwait;" \
  76                 "booti ${loadaddr} - ${fdt_addr}\0" \
  77         "mmcload=mmc rescan;" \
  78                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  79                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  80         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  81                 " root=${mmcroot} rw rootwait;" \
  82                 "bootm ${loadaddr}\0" \
  83         "mmcfitload=mmc rescan;" \
  84                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  85         "linux_qspi_enable=if sf probe; then " \
  86                 "echo Enabling QSPI at Linux DTB...;" \
  87                 "fdt addr ${fdt_addr}; fdt resize;" \
  88                 "fdt set /soc/spi@ff8d2000 status okay;" \
  89                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  90                 " ${qspi_clock}; fi; \0" \
  91         "scriptaddr=0x02100000\0" \
  92         "scriptfile=u-boot.scr\0" \
  93         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  94                    "then source ${scriptaddr}; fi\0" \
  95         "socfpga_legacy_reset_compat=1\0"
  96
  97 /*
  98  * External memory configurations
  99  */
 100 #define PHYS_SDRAM_1                    0x0
 101 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 102 #define CONFIG_SYS_SDRAM_BASE           0
 103
 104 /*
 105  * Serial / UART configurations
 106  */
 107 #define CONFIG_SYS_NS16550_CLK          100000000
 108 #define CONFIG_SYS_NS16550_MEM32
 109
 110 /*
 111  * SDMMC configurations
 112  */
 113 #ifdef CONFIG_CMD_MMC
 114 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 115 #endif
 116 /*
 117  * Flash configurations
 118  */
 119
 120 /* Ethernet on SoC (EMAC) */
 121 #if defined(CONFIG_CMD_NET)
 122 #define CONFIG_DW_ALTDESCRIPTOR
 123 #endif /* CONFIG_CMD_NET */
 124
 125 /*
 126  * L4 Watchdog
 127  */
 128 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 129 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 130 #ifndef __ASSEMBLY__
 131 unsigned int cm_get_l4_sys_free_clk_hz(void);
 132 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 133 #endif
 134 #else
 135 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 136 #endif
 137
 138 /*
 139  * SPL memory layout
 140  *
 141  * On chip RAM
 142  * 0xFFE0_0000 ...... Start of OCRAM
 143  * SPL code, rwdata
 144  * empty space
 145  * 0xFFEx_xxxx ...... Top of stack (grows down)
 146  * 0xFFEy_yyyy ...... Global Data
 147  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 148  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 149  * 0xFFE3_FFFF ...... End of OCRAM
 150  *
 151  * SDRAM
 152  * 0x0000_0000 ...... Start of SDRAM_1
 153  * unused / empty space for image loading
 154  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 155  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 156  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 157  *
 158  */
 159 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 160 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 161 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 162 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 163 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 164                                         - CONFIG_SPL_BSS_MAX_SIZE)
 165 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 166 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 167                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 168
 169 /* SPL SDMMC boot support */
 170 #ifdef CONFIG_SPL_LOAD_FIT
 171 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 172 #else
 173 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 174 #endif
 175
 176 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */