include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_s10.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_LOADADDR                 0x2000000
  19 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  20 #define CONFIG_REMAKE_ELF
  21 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  22 #define CPU_RELEASE_ADDR                0xFFD12210
  23 #define CONFIG_SYS_CACHELINE_SIZE       64
  24 #define CONFIG_SYS_MEM_RESERVE_SECURE   0       /* using OCRAM, not DDR */
  25
  26 /*
  27  * U-Boot console configurations
  28  */
  29 #define CONFIG_SYS_MAXARGS              64
  30 #define CONFIG_SYS_CBSIZE               2048
  31 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  32                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  33 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  34
  35 /* Extend size of kernel image for uncompression */
  36 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  37
  38 /*
  39  * U-Boot run time memory configurations
  40  */
  41 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  42 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  45                                         + CONFIG_SYS_INIT_RAM_SIZE \
  46                                         - SOC64_HANDOFF_SIZE)
  47 #else
  48 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  49                                         + 0x100000)
  50 #endif
  51 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  52 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  53
  54 /*
  55  * U-Boot environment configurations
  56  */
  57
  58 /*
  59  * QSPI support
  60  */
  61  #ifdef CONFIG_CADENCE_QSPI
  62 /* Enable it if you want to use dual-stacked mode */
  63 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  64
  65 /* Flash device info */
  66
  67 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  68
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_MTD_PARTITIONS
  71 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  72 #endif /* CONFIG_SPL_BUILD */
  73
  74 #ifndef __ASSEMBLY__
  75 unsigned int cm_get_qspi_controller_clk_hz(void);
  76 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  77 #endif
  78
  79 #endif /* CONFIG_CADENCE_QSPI */
  80
  81 /*
  82  * Environment variable
  83  */
  84
  85 #ifdef CONFIG_FIT
  86 #define CONFIG_BOOTFILE "kernel.itb"
  87 #else
  88 #define CONFIG_BOOTFILE "Image"
  89 #endif
  90
  91 #define CONFIG_EXTRA_ENV_SETTINGS \
  92         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  93         "bootfile=" CONFIG_BOOTFILE "\0" \
  94         "fdt_addr=8000000\0" \
  95         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  96         "mmcroot=/dev/mmcblk0p2\0" \
  97         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  98                 " root=${mmcroot} rw rootwait;" \
  99                 "booti ${loadaddr} - ${fdt_addr}\0" \
 100         "mmcload=mmc rescan;" \
 101                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
 102                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 103         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 104                 " root=${mmcroot} rw rootwait;" \
 105                 "bootm ${loadaddr}\0" \
 106         "mmcfitload=mmc rescan;" \
 107                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 108         "linux_qspi_enable=if sf probe; then " \
 109                 "echo Enabling QSPI at Linux DTB...;" \
 110                 "fdt addr ${fdt_addr}; fdt resize;" \
 111                 "fdt set /soc/spi@ff8d2000 status okay;" \
 112                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 113                 " ${qspi_clock}; fi; \0" \
 114         "scriptaddr=0x02100000\0" \
 115         "scriptfile=u-boot.scr\0" \
 116         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 117                    "then source ${scriptaddr}; fi\0" \
 118         "socfpga_legacy_reset_compat=1\0"
 119
 120 /*
 121  * Generic Interrupt Controller Definitions
 122  */
 123 #define CONFIG_GICV2
 124
 125 /*
 126  * External memory configurations
 127  */
 128 #define PHYS_SDRAM_1                    0x0
 129 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 130 #define CONFIG_SYS_SDRAM_BASE           0
 131
 132 /*
 133  * Serial / UART configurations
 134  */
 135 #define CONFIG_SYS_NS16550_CLK          100000000
 136 #define CONFIG_SYS_NS16550_MEM32
 137
 138 /*
 139  * Timer & watchdog configurations
 140  */
 141 #define COUNTER_FREQUENCY               400000000
 142
 143 /*
 144  * SDMMC configurations
 145  */
 146 #ifdef CONFIG_CMD_MMC
 147 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 148 #endif
 149 /*
 150  * Flash configurations
 151  */
 152 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 153
 154 /* Ethernet on SoC (EMAC) */
 155 #if defined(CONFIG_CMD_NET)
 156 #define CONFIG_DW_ALTDESCRIPTOR
 157 #endif /* CONFIG_CMD_NET */
 158
 159 /*
 160  * L4 Watchdog
 161  */
 162 #ifndef CONFIG_SPL_BUILD
 163 #undef CONFIG_HW_WATCHDOG
 164 #undef CONFIG_DESIGNWARE_WATCHDOG
 165 #endif
 166 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 167 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 168 #ifndef __ASSEMBLY__
 169 unsigned int cm_get_l4_sys_free_clk_hz(void);
 170 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 171 #endif
 172 #else
 173 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 174 #endif
 175
 176 /*
 177  * SPL memory layout
 178  *
 179  * On chip RAM
 180  * 0xFFE0_0000 ...... Start of OCRAM
 181  * SPL code, rwdata
 182  * empty space
 183  * 0xFFEx_xxxx ...... Top of stack (grows down)
 184  * 0xFFEy_yyyy ...... Global Data
 185  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 186  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 187  * 0xFFE3_FFFF ...... End of OCRAM
 188  *
 189  * SDRAM
 190  * 0x0000_0000 ...... Start of SDRAM_1
 191  * unused / empty space for image loading
 192  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 193  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 194  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 195  *
 196  */
 197 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 198 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 199 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 200 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 201 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 202                                         - CONFIG_SPL_BSS_MAX_SIZE)
 203 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 204 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 205                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 206
 207 /* SPL SDMMC boot support */
 208 #ifdef CONFIG_SPL_LOAD_FIT
 209 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 210 #else
 211 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 212 #endif
 213
 214 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */