include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_s10.h>
  11 #include <asm/arch/handoff_s10.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_LOADADDR                 0x2000000
  19 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  20 #define CONFIG_REMAKE_ELF
  21 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  22 #define CPU_RELEASE_ADDR                0xFFD12210
  23 #define CONFIG_SYS_CACHELINE_SIZE       64
  24 #define CONFIG_SYS_MEM_RESERVE_SECURE   0       /* using OCRAM, not DDR */
  25
  26 /*
  27  * U-Boot console configurations
  28  */
  29 #define CONFIG_SYS_MAXARGS              64
  30 #define CONFIG_SYS_CBSIZE               2048
  31 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  32                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  33 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  34
  35 /* Extend size of kernel image for uncompression */
  36 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  37
  38 /*
  39  * U-Boot run time memory configurations
  40  */
  41 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  42 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  45                                         + CONFIG_SYS_INIT_RAM_SIZE \
  46                                         - S10_HANDOFF_SIZE)
  47 #else
  48 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  49                                         + 0x100000)
  50 #endif
  51 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  52 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  53
  54 /*
  55  * U-Boot environment configurations
  56  */
  57
  58 /*
  59  * QSPI support
  60  */
  61  #ifdef CONFIG_CADENCE_QSPI
  62 /* Enable it if you want to use dual-stacked mode */
  63 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  64
  65 /* Flash device info */
  66
  67 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  68
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_MTD_PARTITIONS
  71 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  72 #endif /* CONFIG_SPL_BUILD */
  73
  74 #ifndef __ASSEMBLY__
  75 unsigned int cm_get_qspi_controller_clk_hz(void);
  76 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  77 #endif
  78
  79 #endif /* CONFIG_CADENCE_QSPI */
  80
  81 /*
  82  * Boot arguments passed to the boot command. The value of
  83  * CONFIG_BOOTARGS goes into the environment value "bootargs".
  84  * Do note the value will override also the chosen node in FDT blob.
  85  */
  86
  87 #ifdef CONFIG_FIT
  88 #define CONFIG_BOOTFILE "kernel.itb"
  89 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \
  90                            "run mmcfitboot"
  91 #else
  92 #define CONFIG_BOOTFILE "Image"
  93 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  94                            "run mmcboot"
  95 #endif
  96
  97 #define CONFIG_EXTRA_ENV_SETTINGS \
  98         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  99         "bootfile=" CONFIG_BOOTFILE "\0" \
 100         "fdt_addr=8000000\0" \
 101         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 102         "mmcroot=/dev/mmcblk0p2\0" \
 103         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
 104                 " root=${mmcroot} rw rootwait;" \
 105                 "booti ${loadaddr} - ${fdt_addr}\0" \
 106         "mmcload=mmc rescan;" \
 107                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
 108                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 109         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 110                 " root=${mmcroot} rw rootwait;" \
 111                 "bootm ${loadaddr}\0" \
 112         "mmcfitload=mmc rescan;" \
 113                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 114         "linux_qspi_enable=if sf probe; then " \
 115                 "echo Enabling QSPI at Linux DTB...;" \
 116                 "fdt addr ${fdt_addr}; fdt resize;" \
 117                 "fdt set /soc/spi@ff8d2000 status okay;" \
 118                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 119                 " ${qspi_clock}; fi; \0" \
 120         "scriptaddr=0x02100000\0" \
 121         "scriptfile=u-boot.scr\0" \
 122         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 123                    "then source ${scriptaddr}; fi\0" \
 124         "socfpga_legacy_reset_compat=1\0"
 125
 126 /*
 127  * Generic Interrupt Controller Definitions
 128  */
 129 #define CONFIG_GICV2
 130
 131 /*
 132  * External memory configurations
 133  */
 134 #define PHYS_SDRAM_1                    0x0
 135 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 136 #define CONFIG_SYS_SDRAM_BASE           0
 137
 138 /*
 139  * Serial / UART configurations
 140  */
 141 #define CONFIG_SYS_NS16550_CLK          100000000
 142 #define CONFIG_SYS_NS16550_MEM32
 143
 144 /*
 145  * Timer & watchdog configurations
 146  */
 147 #define COUNTER_FREQUENCY               400000000
 148
 149 /*
 150  * SDMMC configurations
 151  */
 152 #ifdef CONFIG_CMD_MMC
 153 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 154 #endif
 155 /*
 156  * Flash configurations
 157  */
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 159
 160 /* Ethernet on SoC (EMAC) */
 161 #if defined(CONFIG_CMD_NET)
 162 #define CONFIG_DW_ALTDESCRIPTOR
 163 #endif /* CONFIG_CMD_NET */
 164
 165 /*
 166  * L4 Watchdog
 167  */
 168 #ifndef CONFIG_SPL_BUILD
 169 #undef CONFIG_HW_WATCHDOG
 170 #undef CONFIG_DESIGNWARE_WATCHDOG
 171 #endif
 172 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 173 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 174 #ifndef __ASSEMBLY__
 175 unsigned int cm_get_l4_sys_free_clk_hz(void);
 176 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 177 #endif
 178 #else
 179 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 180 #endif
 181
 182 /*
 183  * SPL memory layout
 184  *
 185  * On chip RAM
 186  * 0xFFE0_0000 ...... Start of OCRAM
 187  * SPL code, rwdata
 188  * empty space
 189  * 0xFFEx_xxxx ...... Top of stack (grows down)
 190  * 0xFFEy_yyyy ...... Global Data
 191  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 192  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 193  * 0xFFE3_FFFF ...... End of OCRAM
 194  *
 195  * SDRAM
 196  * 0x0000_0000 ...... Start of SDRAM_1
 197  * unused / empty space for image loading
 198  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 199  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 200  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 201  *
 202  */
 203 #define CONFIG_SPL_TARGET               "spl/u-boot-spl.hex"
 204 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 205 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 206 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 207 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 208                                         - CONFIG_SPL_BSS_MAX_SIZE)
 209 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 210 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 211                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 212
 213 /* SPL SDMMC boot support */
 214 #ifdef CONFIG_SPL_LOAD_FIT
 215 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 216 #else
 217 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 218 #endif
 219
 220 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */