include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_LOADADDR                 0x2000000
  19 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  20 #define CONFIG_REMAKE_ELF
  21 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  22 #define CPU_RELEASE_ADDR                0xFFD12210
  23
  24 /*
  25  * U-Boot console configurations
  26  */
  27 #define CONFIG_SYS_MAXARGS              64
  28 #define CONFIG_SYS_CBSIZE               2048
  29 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  30                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  31 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  32
  33 /* Extend size of kernel image for uncompression */
  34 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  35
  36 /*
  37  * U-Boot run time memory configurations
  38  */
  39 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  40 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  43                                         + CONFIG_SYS_INIT_RAM_SIZE \
  44                                         - SOC64_HANDOFF_SIZE)
  45 #else
  46 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  47                                         + 0x100000)
  48 #endif
  49 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  50 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  51
  52 /*
  53  * U-Boot environment configurations
  54  */
  55
  56 /*
  57  * QSPI support
  58  */
  59  #ifdef CONFIG_CADENCE_QSPI
  60 /* Enable it if you want to use dual-stacked mode */
  61 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  62
  63 /* Flash device info */
  64
  65 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  66
  67 #ifndef CONFIG_SPL_BUILD
  68 #define CONFIG_MTD_PARTITIONS
  69 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  70 #endif /* CONFIG_SPL_BUILD */
  71
  72 #ifndef __ASSEMBLY__
  73 unsigned int cm_get_qspi_controller_clk_hz(void);
  74 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  75 #endif
  76
  77 #endif /* CONFIG_CADENCE_QSPI */
  78
  79 /*
  80  * Environment variable
  81  */
  82
  83 #ifdef CONFIG_FIT
  84 #define CONFIG_BOOTFILE "kernel.itb"
  85 #else
  86 #define CONFIG_BOOTFILE "Image"
  87 #endif
  88
  89 #define CONFIG_EXTRA_ENV_SETTINGS \
  90         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  91         "bootfile=" CONFIG_BOOTFILE "\0" \
  92         "fdt_addr=8000000\0" \
  93         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  94         "mmcroot=/dev/mmcblk0p2\0" \
  95         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  96                 " root=${mmcroot} rw rootwait;" \
  97                 "booti ${loadaddr} - ${fdt_addr}\0" \
  98         "mmcload=mmc rescan;" \
  99                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
 100                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 101         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 102                 " root=${mmcroot} rw rootwait;" \
 103                 "bootm ${loadaddr}\0" \
 104         "mmcfitload=mmc rescan;" \
 105                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 106         "linux_qspi_enable=if sf probe; then " \
 107                 "echo Enabling QSPI at Linux DTB...;" \
 108                 "fdt addr ${fdt_addr}; fdt resize;" \
 109                 "fdt set /soc/spi@ff8d2000 status okay;" \
 110                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 111                 " ${qspi_clock}; fi; \0" \
 112         "scriptaddr=0x02100000\0" \
 113         "scriptfile=u-boot.scr\0" \
 114         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 115                    "then source ${scriptaddr}; fi\0" \
 116         "socfpga_legacy_reset_compat=1\0"
 117
 118 /*
 119  * External memory configurations
 120  */
 121 #define PHYS_SDRAM_1                    0x0
 122 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 123 #define CONFIG_SYS_SDRAM_BASE           0
 124
 125 /*
 126  * Serial / UART configurations
 127  */
 128 #define CONFIG_SYS_NS16550_CLK          100000000
 129 #define CONFIG_SYS_NS16550_MEM32
 130
 131 /*
 132  * Timer & watchdog configurations
 133  */
 134 #define COUNTER_FREQUENCY               400000000
 135
 136 /*
 137  * SDMMC configurations
 138  */
 139 #ifdef CONFIG_CMD_MMC
 140 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 141 #endif
 142 /*
 143  * Flash configurations
 144  */
 145 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 146
 147 /* Ethernet on SoC (EMAC) */
 148 #if defined(CONFIG_CMD_NET)
 149 #define CONFIG_DW_ALTDESCRIPTOR
 150 #endif /* CONFIG_CMD_NET */
 151
 152 /*
 153  * L4 Watchdog
 154  */
 155 #ifndef CONFIG_SPL_BUILD
 156 #undef CONFIG_HW_WATCHDOG
 157 #undef CONFIG_DESIGNWARE_WATCHDOG
 158 #endif
 159 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 160 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 161 #ifndef __ASSEMBLY__
 162 unsigned int cm_get_l4_sys_free_clk_hz(void);
 163 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 164 #endif
 165 #else
 166 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 167 #endif
 168
 169 /*
 170  * SPL memory layout
 171  *
 172  * On chip RAM
 173  * 0xFFE0_0000 ...... Start of OCRAM
 174  * SPL code, rwdata
 175  * empty space
 176  * 0xFFEx_xxxx ...... Top of stack (grows down)
 177  * 0xFFEy_yyyy ...... Global Data
 178  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 179  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 180  * 0xFFE3_FFFF ...... End of OCRAM
 181  *
 182  * SDRAM
 183  * 0x0000_0000 ...... Start of SDRAM_1
 184  * unused / empty space for image loading
 185  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 186  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 187  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 188  *
 189  */
 190 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 191 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 192 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 193 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 194 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 195                                         - CONFIG_SPL_BSS_MAX_SIZE)
 196 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 197 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 198                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 199
 200 /* SPL SDMMC boot support */
 201 #ifdef CONFIG_SPL_LOAD_FIT
 202 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 203 #else
 204 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 205 #endif
 206
 207 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */