include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23
  24 /* Extend size of kernel image for uncompression */
  25
  26 /*
  27  * U-Boot run time memory configurations
  28  */
  29 #define CFG_SYS_INIT_RAM_ADDR   0xFFE00000
  30 #define CFG_SYS_INIT_RAM_SIZE   0x40000
  31
  32 /*
  33  * U-Boot environment configurations
  34  */
  35
  36 /*
  37  * Environment variable
  38  */
  39 #define CFG_EXTRA_ENV_SETTINGS \
  40         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  41         "bootfile=" CONFIG_BOOTFILE "\0" \
  42         "fdt_addr=8000000\0" \
  43         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  44         "mmcroot=/dev/mmcblk0p2\0" \
  45         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  46                 " root=${mmcroot} rw rootwait;" \
  47                 "booti ${loadaddr} - ${fdt_addr}\0" \
  48         "mmcload=mmc rescan;" \
  49                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  50                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  51         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  52                 " root=${mmcroot} rw rootwait;" \
  53                 "bootm ${loadaddr}\0" \
  54         "mmcfitload=mmc rescan;" \
  55                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  56         "linux_qspi_enable=if sf probe; then " \
  57                 "echo Enabling QSPI at Linux DTB...;" \
  58                 "fdt addr ${fdt_addr}; fdt resize;" \
  59                 "fdt set /soc/spi@ff8d2000 status okay;" \
  60                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  61                 " ${qspi_clock}; fi; \0" \
  62         "scriptaddr=0x02100000\0" \
  63         "scriptfile=u-boot.scr\0" \
  64         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  65                    "then source ${scriptaddr}; fi\0" \
  66         "socfpga_legacy_reset_compat=1\0"
  67
  68 /*
  69  * External memory configurations
  70  */
  71 #define PHYS_SDRAM_1                    0x0
  72 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
  73 #define CFG_SYS_SDRAM_BASE              0
  74
  75 /*
  76  * Serial / UART configurations
  77  */
  78 #define CFG_SYS_NS16550_CLK             100000000
  79
  80 /*
  81  * SDMMC configurations
  82  */
  83 /*
  84  * Flash configurations
  85  */
  86
  87 /*
  88  * L4 Watchdog
  89  */
  90 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
  91 #ifndef __ASSEMBLY__
  92 unsigned int cm_get_l4_sys_free_clk_hz(void);
  93 #define CFG_DW_WDT_CLOCK_KHZ            (cm_get_l4_sys_free_clk_hz() / 1000)
  94 #endif
  95 #else
  96 #define CFG_DW_WDT_CLOCK_KHZ            100000
  97 #endif
  98
  99 /*
 100  * SPL memory layout
 101  *
 102  * On chip RAM
 103  * 0xFFE0_0000 ...... Start of OCRAM
 104  * SPL code, rwdata
 105  * empty space
 106  * 0xFFEx_xxxx ...... Top of stack (grows down)
 107  * 0xFFEy_yyyy ...... Global Data
 108  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 109  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 110  * 0xFFE3_FFFF ...... End of OCRAM
 111  *
 112  * SDRAM
 113  * 0x0000_0000 ...... Start of SDRAM_1
 114  * unused / empty space for image loading
 115  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 116  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 117  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 118  *
 119  */
 120
 121 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */