include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23
  24 /* Extend size of kernel image for uncompression */
  25 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  26
  27 /*
  28  * U-Boot run time memory configurations
  29  */
  30 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  31 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  32 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  33                                         + 0x100000)
  34 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  35
  36 /*
  37  * U-Boot environment configurations
  38  */
  39
  40 /*
  41  * QSPI support
  42  */
  43  #ifdef CONFIG_CADENCE_QSPI
  44 /* Enable it if you want to use dual-stacked mode */
  45 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  46
  47 /* Flash device info */
  48
  49 #ifndef CONFIG_SPL_BUILD
  50 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  51 #endif /* CONFIG_SPL_BUILD */
  52
  53 #endif /* CONFIG_CADENCE_QSPI */
  54
  55 /*
  56  * Environment variable
  57  */
  58 #define CONFIG_EXTRA_ENV_SETTINGS \
  59         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  60         "bootfile=" CONFIG_BOOTFILE "\0" \
  61         "fdt_addr=8000000\0" \
  62         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  63         "mmcroot=/dev/mmcblk0p2\0" \
  64         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  65                 " root=${mmcroot} rw rootwait;" \
  66                 "booti ${loadaddr} - ${fdt_addr}\0" \
  67         "mmcload=mmc rescan;" \
  68                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  69                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  70         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  71                 " root=${mmcroot} rw rootwait;" \
  72                 "bootm ${loadaddr}\0" \
  73         "mmcfitload=mmc rescan;" \
  74                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  75         "linux_qspi_enable=if sf probe; then " \
  76                 "echo Enabling QSPI at Linux DTB...;" \
  77                 "fdt addr ${fdt_addr}; fdt resize;" \
  78                 "fdt set /soc/spi@ff8d2000 status okay;" \
  79                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  80                 " ${qspi_clock}; fi; \0" \
  81         "scriptaddr=0x02100000\0" \
  82         "scriptfile=u-boot.scr\0" \
  83         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  84                    "then source ${scriptaddr}; fi\0" \
  85         "socfpga_legacy_reset_compat=1\0"
  86
  87 /*
  88  * External memory configurations
  89  */
  90 #define PHYS_SDRAM_1                    0x0
  91 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
  92 #define CONFIG_SYS_SDRAM_BASE           0
  93
  94 /*
  95  * Serial / UART configurations
  96  */
  97 #define CONFIG_SYS_NS16550_CLK          100000000
  98 #define CONFIG_SYS_NS16550_MEM32
  99
 100 /*
 101  * SDMMC configurations
 102  */
 103 #ifdef CONFIG_CMD_MMC
 104 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 105 #endif
 106 /*
 107  * Flash configurations
 108  */
 109
 110 /* Ethernet on SoC (EMAC) */
 111 #if defined(CONFIG_CMD_NET)
 112 #define CONFIG_DW_ALTDESCRIPTOR
 113 #endif /* CONFIG_CMD_NET */
 114
 115 /*
 116  * L4 Watchdog
 117  */
 118 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 119 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 120 #ifndef __ASSEMBLY__
 121 unsigned int cm_get_l4_sys_free_clk_hz(void);
 122 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 123 #endif
 124 #else
 125 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 126 #endif
 127
 128 /*
 129  * SPL memory layout
 130  *
 131  * On chip RAM
 132  * 0xFFE0_0000 ...... Start of OCRAM
 133  * SPL code, rwdata
 134  * empty space
 135  * 0xFFEx_xxxx ...... Top of stack (grows down)
 136  * 0xFFEy_yyyy ...... Global Data
 137  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 138  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 139  * 0xFFE3_FFFF ...... End of OCRAM
 140  *
 141  * SDRAM
 142  * 0x0000_0000 ...... Start of SDRAM_1
 143  * unused / empty space for image loading
 144  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 145  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 146  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 147  *
 148  */
 149 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 150 #define CONFIG_SPL_STACK                (CONFIG_SYS_INIT_RAM_ADDR  \
 151                                         + CONFIG_SYS_INIT_RAM_SIZE \
 152                                         - SOC64_HANDOFF_SIZE)
 153 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 154                                         - CONFIG_SPL_BSS_MAX_SIZE)
 155 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 156 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 157                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 158
 159 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */