include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_s10.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_LOADADDR                 0x2000000
  19 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  20 #define CONFIG_REMAKE_ELF
  21 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  22 #define CPU_RELEASE_ADDR                0xFFD12210
  23 #define CONFIG_SYS_CACHELINE_SIZE       64
  24
  25 /*
  26  * U-Boot console configurations
  27  */
  28 #define CONFIG_SYS_MAXARGS              64
  29 #define CONFIG_SYS_CBSIZE               2048
  30 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  31                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  32 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  33
  34 /* Extend size of kernel image for uncompression */
  35 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  36
  37 /*
  38  * U-Boot run time memory configurations
  39  */
  40 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  41 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  44                                         + CONFIG_SYS_INIT_RAM_SIZE \
  45                                         - SOC64_HANDOFF_SIZE)
  46 #else
  47 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  48                                         + 0x100000)
  49 #endif
  50 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  51 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  52
  53 /*
  54  * U-Boot environment configurations
  55  */
  56
  57 /*
  58  * QSPI support
  59  */
  60  #ifdef CONFIG_CADENCE_QSPI
  61 /* Enable it if you want to use dual-stacked mode */
  62 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  63
  64 /* Flash device info */
  65
  66 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  67
  68 #ifndef CONFIG_SPL_BUILD
  69 #define CONFIG_MTD_PARTITIONS
  70 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  71 #endif /* CONFIG_SPL_BUILD */
  72
  73 #ifndef __ASSEMBLY__
  74 unsigned int cm_get_qspi_controller_clk_hz(void);
  75 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  76 #endif
  77
  78 #endif /* CONFIG_CADENCE_QSPI */
  79
  80 /*
  81  * Environment variable
  82  */
  83
  84 #ifdef CONFIG_FIT
  85 #define CONFIG_BOOTFILE "kernel.itb"
  86 #else
  87 #define CONFIG_BOOTFILE "Image"
  88 #endif
  89
  90 #define CONFIG_EXTRA_ENV_SETTINGS \
  91         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  92         "bootfile=" CONFIG_BOOTFILE "\0" \
  93         "fdt_addr=8000000\0" \
  94         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  95         "mmcroot=/dev/mmcblk0p2\0" \
  96         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  97                 " root=${mmcroot} rw rootwait;" \
  98                 "booti ${loadaddr} - ${fdt_addr}\0" \
  99         "mmcload=mmc rescan;" \
 100                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
 101                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 102         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 103                 " root=${mmcroot} rw rootwait;" \
 104                 "bootm ${loadaddr}\0" \
 105         "mmcfitload=mmc rescan;" \
 106                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 107         "linux_qspi_enable=if sf probe; then " \
 108                 "echo Enabling QSPI at Linux DTB...;" \
 109                 "fdt addr ${fdt_addr}; fdt resize;" \
 110                 "fdt set /soc/spi@ff8d2000 status okay;" \
 111                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 112                 " ${qspi_clock}; fi; \0" \
 113         "scriptaddr=0x02100000\0" \
 114         "scriptfile=u-boot.scr\0" \
 115         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 116                    "then source ${scriptaddr}; fi\0" \
 117         "socfpga_legacy_reset_compat=1\0"
 118
 119 /*
 120  * Generic Interrupt Controller Definitions
 121  */
 122 #define CONFIG_GICV2
 123
 124 /*
 125  * External memory configurations
 126  */
 127 #define PHYS_SDRAM_1                    0x0
 128 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 129 #define CONFIG_SYS_SDRAM_BASE           0
 130
 131 /*
 132  * Serial / UART configurations
 133  */
 134 #define CONFIG_SYS_NS16550_CLK          100000000
 135 #define CONFIG_SYS_NS16550_MEM32
 136
 137 /*
 138  * Timer & watchdog configurations
 139  */
 140 #define COUNTER_FREQUENCY               400000000
 141
 142 /*
 143  * SDMMC configurations
 144  */
 145 #ifdef CONFIG_CMD_MMC
 146 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 147 #endif
 148 /*
 149  * Flash configurations
 150  */
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 152
 153 /* Ethernet on SoC (EMAC) */
 154 #if defined(CONFIG_CMD_NET)
 155 #define CONFIG_DW_ALTDESCRIPTOR
 156 #endif /* CONFIG_CMD_NET */
 157
 158 /*
 159  * L4 Watchdog
 160  */
 161 #ifndef CONFIG_SPL_BUILD
 162 #undef CONFIG_HW_WATCHDOG
 163 #undef CONFIG_DESIGNWARE_WATCHDOG
 164 #endif
 165 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 166 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 167 #ifndef __ASSEMBLY__
 168 unsigned int cm_get_l4_sys_free_clk_hz(void);
 169 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 170 #endif
 171 #else
 172 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 173 #endif
 174
 175 /*
 176  * SPL memory layout
 177  *
 178  * On chip RAM
 179  * 0xFFE0_0000 ...... Start of OCRAM
 180  * SPL code, rwdata
 181  * empty space
 182  * 0xFFEx_xxxx ...... Top of stack (grows down)
 183  * 0xFFEy_yyyy ...... Global Data
 184  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 185  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 186  * 0xFFE3_FFFF ...... End of OCRAM
 187  *
 188  * SDRAM
 189  * 0x0000_0000 ...... Start of SDRAM_1
 190  * unused / empty space for image loading
 191  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 192  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 193  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 194  *
 195  */
 196 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 197 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 198 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 199 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 200 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 201                                         - CONFIG_SPL_BSS_MAX_SIZE)
 202 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 203 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 204                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 205
 206 /* SPL SDMMC boot support */
 207 #ifdef CONFIG_SPL_LOAD_FIT
 208 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 209 #else
 210 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 211 #endif
 212
 213 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */