include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23 #define CONFIG_SYS_MAXARGS              64
  24 #define CONFIG_SYS_CBSIZE               2048
  25 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  26                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  27 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  28
  29 /* Extend size of kernel image for uncompression */
  30 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  31
  32 /*
  33  * U-Boot run time memory configurations
  34  */
  35 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  36 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  39                                         + CONFIG_SYS_INIT_RAM_SIZE \
  40                                         - SOC64_HANDOFF_SIZE)
  41 #else
  42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  43                                         + 0x100000)
  44 #endif
  45 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  46
  47 /*
  48  * U-Boot environment configurations
  49  */
  50
  51 /*
  52  * QSPI support
  53  */
  54  #ifdef CONFIG_CADENCE_QSPI
  55 /* Enable it if you want to use dual-stacked mode */
  56 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  57
  58 /* Flash device info */
  59
  60 #ifndef CONFIG_SPL_BUILD
  61 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  62 #endif /* CONFIG_SPL_BUILD */
  63
  64 #endif /* CONFIG_CADENCE_QSPI */
  65
  66 /*
  67  * Environment variable
  68  */
  69 #define CONFIG_EXTRA_ENV_SETTINGS \
  70         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  71         "bootfile=" CONFIG_BOOTFILE "\0" \
  72         "fdt_addr=8000000\0" \
  73         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  74         "mmcroot=/dev/mmcblk0p2\0" \
  75         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  76                 " root=${mmcroot} rw rootwait;" \
  77                 "booti ${loadaddr} - ${fdt_addr}\0" \
  78         "mmcload=mmc rescan;" \
  79                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  80                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  81         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  82                 " root=${mmcroot} rw rootwait;" \
  83                 "bootm ${loadaddr}\0" \
  84         "mmcfitload=mmc rescan;" \
  85                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  86         "linux_qspi_enable=if sf probe; then " \
  87                 "echo Enabling QSPI at Linux DTB...;" \
  88                 "fdt addr ${fdt_addr}; fdt resize;" \
  89                 "fdt set /soc/spi@ff8d2000 status okay;" \
  90                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  91                 " ${qspi_clock}; fi; \0" \
  92         "scriptaddr=0x02100000\0" \
  93         "scriptfile=u-boot.scr\0" \
  94         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  95                    "then source ${scriptaddr}; fi\0" \
  96         "socfpga_legacy_reset_compat=1\0"
  97
  98 /*
  99  * External memory configurations
 100  */
 101 #define PHYS_SDRAM_1                    0x0
 102 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 103 #define CONFIG_SYS_SDRAM_BASE           0
 104
 105 /*
 106  * Serial / UART configurations
 107  */
 108 #define CONFIG_SYS_NS16550_CLK          100000000
 109 #define CONFIG_SYS_NS16550_MEM32
 110
 111 /*
 112  * Timer & watchdog configurations
 113  */
 114 #define COUNTER_FREQUENCY               400000000
 115
 116 /*
 117  * SDMMC configurations
 118  */
 119 #ifdef CONFIG_CMD_MMC
 120 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 121 #endif
 122 /*
 123  * Flash configurations
 124  */
 125
 126 /* Ethernet on SoC (EMAC) */
 127 #if defined(CONFIG_CMD_NET)
 128 #define CONFIG_DW_ALTDESCRIPTOR
 129 #endif /* CONFIG_CMD_NET */
 130
 131 /*
 132  * L4 Watchdog
 133  */
 134 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 135 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 136 #ifndef __ASSEMBLY__
 137 unsigned int cm_get_l4_sys_free_clk_hz(void);
 138 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 139 #endif
 140 #else
 141 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 142 #endif
 143
 144 /*
 145  * SPL memory layout
 146  *
 147  * On chip RAM
 148  * 0xFFE0_0000 ...... Start of OCRAM
 149  * SPL code, rwdata
 150  * empty space
 151  * 0xFFEx_xxxx ...... Top of stack (grows down)
 152  * 0xFFEy_yyyy ...... Global Data
 153  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 154  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 155  * 0xFFE3_FFFF ...... End of OCRAM
 156  *
 157  * SDRAM
 158  * 0x0000_0000 ...... Start of SDRAM_1
 159  * unused / empty space for image loading
 160  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 161  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 162  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 163  *
 164  */
 165 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 166 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 167 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 168 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 169 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 170                                         - CONFIG_SPL_BSS_MAX_SIZE)
 171 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 172 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 173                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 174
 175 /* SPL SDMMC boot support */
 176 #ifdef CONFIG_SPL_LOAD_FIT
 177 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 178 #else
 179 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 180 #endif
 181
 182 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */