include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23 #define CONFIG_SYS_MAXARGS              64
  24 #define CONFIG_SYS_CBSIZE               2048
  25 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  26                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  27 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  28
  29 /* Extend size of kernel image for uncompression */
  30 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  31
  32 /*
  33  * U-Boot run time memory configurations
  34  */
  35 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  36 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  39                                         + CONFIG_SYS_INIT_RAM_SIZE \
  40                                         - SOC64_HANDOFF_SIZE)
  41 #else
  42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  43                                         + 0x100000)
  44 #endif
  45 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  46
  47 /*
  48  * U-Boot environment configurations
  49  */
  50
  51 /*
  52  * QSPI support
  53  */
  54  #ifdef CONFIG_CADENCE_QSPI
  55 /* Enable it if you want to use dual-stacked mode */
  56 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  57
  58 /* Flash device info */
  59
  60 #ifndef CONFIG_SPL_BUILD
  61 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  62 #endif /* CONFIG_SPL_BUILD */
  63
  64 #ifndef __ASSEMBLY__
  65 unsigned int cm_get_qspi_controller_clk_hz(void);
  66 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  67 #endif
  68
  69 #endif /* CONFIG_CADENCE_QSPI */
  70
  71 /*
  72  * Environment variable
  73  */
  74 #define CONFIG_EXTRA_ENV_SETTINGS \
  75         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  76         "bootfile=" CONFIG_BOOTFILE "\0" \
  77         "fdt_addr=8000000\0" \
  78         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  79         "mmcroot=/dev/mmcblk0p2\0" \
  80         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  81                 " root=${mmcroot} rw rootwait;" \
  82                 "booti ${loadaddr} - ${fdt_addr}\0" \
  83         "mmcload=mmc rescan;" \
  84                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  85                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  86         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  87                 " root=${mmcroot} rw rootwait;" \
  88                 "bootm ${loadaddr}\0" \
  89         "mmcfitload=mmc rescan;" \
  90                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  91         "linux_qspi_enable=if sf probe; then " \
  92                 "echo Enabling QSPI at Linux DTB...;" \
  93                 "fdt addr ${fdt_addr}; fdt resize;" \
  94                 "fdt set /soc/spi@ff8d2000 status okay;" \
  95                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  96                 " ${qspi_clock}; fi; \0" \
  97         "scriptaddr=0x02100000\0" \
  98         "scriptfile=u-boot.scr\0" \
  99         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 100                    "then source ${scriptaddr}; fi\0" \
 101         "socfpga_legacy_reset_compat=1\0"
 102
 103 /*
 104  * External memory configurations
 105  */
 106 #define PHYS_SDRAM_1                    0x0
 107 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 108 #define CONFIG_SYS_SDRAM_BASE           0
 109
 110 /*
 111  * Serial / UART configurations
 112  */
 113 #define CONFIG_SYS_NS16550_CLK          100000000
 114 #define CONFIG_SYS_NS16550_MEM32
 115
 116 /*
 117  * Timer & watchdog configurations
 118  */
 119 #define COUNTER_FREQUENCY               400000000
 120
 121 /*
 122  * SDMMC configurations
 123  */
 124 #ifdef CONFIG_CMD_MMC
 125 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 126 #endif
 127 /*
 128  * Flash configurations
 129  */
 130
 131 /* Ethernet on SoC (EMAC) */
 132 #if defined(CONFIG_CMD_NET)
 133 #define CONFIG_DW_ALTDESCRIPTOR
 134 #endif /* CONFIG_CMD_NET */
 135
 136 /*
 137  * L4 Watchdog
 138  */
 139 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 140 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 141 #ifndef __ASSEMBLY__
 142 unsigned int cm_get_l4_sys_free_clk_hz(void);
 143 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 144 #endif
 145 #else
 146 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 147 #endif
 148
 149 /*
 150  * SPL memory layout
 151  *
 152  * On chip RAM
 153  * 0xFFE0_0000 ...... Start of OCRAM
 154  * SPL code, rwdata
 155  * empty space
 156  * 0xFFEx_xxxx ...... Top of stack (grows down)
 157  * 0xFFEy_yyyy ...... Global Data
 158  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 159  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 160  * 0xFFE3_FFFF ...... End of OCRAM
 161  *
 162  * SDRAM
 163  * 0x0000_0000 ...... Start of SDRAM_1
 164  * unused / empty space for image loading
 165  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 166  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 167  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 168  *
 169  */
 170 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 171 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 172 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 173 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 174 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 175                                         - CONFIG_SPL_BSS_MAX_SIZE)
 176 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 177 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 178                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 179
 180 /* SPL SDMMC boot support */
 181 #ifdef CONFIG_SPL_LOAD_FIT
 182 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 183 #else
 184 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 185 #endif
 186
 187 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */