1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
10 #include <asm/arch/base_addr_soc64.h>
11 #include <asm/arch/handoff_soc64.h>
12 #include <linux/stringify.h>
15 * U-Boot general configurations
17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
18 #define CPU_RELEASE_ADDR 0xFFD12210
21 * U-Boot console configurations
24 /* Extend size of kernel image for uncompression */
25 #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
28 * U-Boot run time memory configurations
30 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
31 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
34 * U-Boot environment configurations
38 * Environment variable
40 #define CONFIG_EXTRA_ENV_SETTINGS \
41 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
42 "bootfile=" CONFIG_BOOTFILE "\0" \
43 "fdt_addr=8000000\0" \
44 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
45 "mmcroot=/dev/mmcblk0p2\0" \
46 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
47 " root=${mmcroot} rw rootwait;" \
48 "booti ${loadaddr} - ${fdt_addr}\0" \
49 "mmcload=mmc rescan;" \
50 "load mmc 0:1 ${loadaddr} ${bootfile};" \
51 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
52 "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
53 " root=${mmcroot} rw rootwait;" \
54 "bootm ${loadaddr}\0" \
55 "mmcfitload=mmc rescan;" \
56 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
57 "linux_qspi_enable=if sf probe; then " \
58 "echo Enabling QSPI at Linux DTB...;" \
59 "fdt addr ${fdt_addr}; fdt resize;" \
60 "fdt set /soc/spi@ff8d2000 status okay;" \
61 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
62 " ${qspi_clock}; fi; \0" \
63 "scriptaddr=0x02100000\0" \
64 "scriptfile=u-boot.scr\0" \
65 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
66 "then source ${scriptaddr}; fi\0" \
67 "socfpga_legacy_reset_compat=1\0"
70 * External memory configurations
72 #define PHYS_SDRAM_1 0x0
73 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
74 #define CONFIG_SYS_SDRAM_BASE 0
77 * Serial / UART configurations
79 #define CONFIG_SYS_NS16550_CLK 100000000
80 #define CONFIG_SYS_NS16550_MEM32
83 * SDMMC configurations
86 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
89 * Flash configurations
95 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
97 unsigned int cm_get_l4_sys_free_clk_hz(void);
98 #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
101 #define CONFIG_DW_WDT_CLOCK_KHZ 100000
108 * 0xFFE0_0000 ...... Start of OCRAM
111 * 0xFFEx_xxxx ...... Top of stack (grows down)
112 * 0xFFEy_yyyy ...... Global Data
113 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
114 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
115 * 0xFFE3_FFFF ...... End of OCRAM
118 * 0x0000_0000 ...... Start of SDRAM_1
119 * unused / empty space for image loading
120 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
121 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
122 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
126 #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */