include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_REMAKE_ELF
  19 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  20 #define CPU_RELEASE_ADDR                0xFFD12210
  21
  22 /*
  23  * U-Boot console configurations
  24  */
  25 #define CONFIG_SYS_MAXARGS              64
  26 #define CONFIG_SYS_CBSIZE               2048
  27 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  28                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  29 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  30
  31 /* Extend size of kernel image for uncompression */
  32 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  33
  34 /*
  35  * U-Boot run time memory configurations
  36  */
  37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  41                                         + CONFIG_SYS_INIT_RAM_SIZE \
  42                                         - SOC64_HANDOFF_SIZE)
  43 #else
  44 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  45                                         + 0x100000)
  46 #endif
  47 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  48 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  49
  50 /*
  51  * U-Boot environment configurations
  52  */
  53
  54 /*
  55  * QSPI support
  56  */
  57  #ifdef CONFIG_CADENCE_QSPI
  58 /* Enable it if you want to use dual-stacked mode */
  59 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  60
  61 /* Flash device info */
  62
  63 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  64
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_MTD_PARTITIONS
  67 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  68 #endif /* CONFIG_SPL_BUILD */
  69
  70 #ifndef __ASSEMBLY__
  71 unsigned int cm_get_qspi_controller_clk_hz(void);
  72 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  73 #endif
  74
  75 #endif /* CONFIG_CADENCE_QSPI */
  76
  77 /*
  78  * Environment variable
  79  */
  80
  81 #ifdef CONFIG_FIT
  82 #define CONFIG_BOOTFILE "kernel.itb"
  83 #else
  84 #define CONFIG_BOOTFILE "Image"
  85 #endif
  86
  87 #define CONFIG_EXTRA_ENV_SETTINGS \
  88         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  89         "bootfile=" CONFIG_BOOTFILE "\0" \
  90         "fdt_addr=8000000\0" \
  91         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  92         "mmcroot=/dev/mmcblk0p2\0" \
  93         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  94                 " root=${mmcroot} rw rootwait;" \
  95                 "booti ${loadaddr} - ${fdt_addr}\0" \
  96         "mmcload=mmc rescan;" \
  97                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  98                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  99         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 100                 " root=${mmcroot} rw rootwait;" \
 101                 "bootm ${loadaddr}\0" \
 102         "mmcfitload=mmc rescan;" \
 103                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 104         "linux_qspi_enable=if sf probe; then " \
 105                 "echo Enabling QSPI at Linux DTB...;" \
 106                 "fdt addr ${fdt_addr}; fdt resize;" \
 107                 "fdt set /soc/spi@ff8d2000 status okay;" \
 108                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 109                 " ${qspi_clock}; fi; \0" \
 110         "scriptaddr=0x02100000\0" \
 111         "scriptfile=u-boot.scr\0" \
 112         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 113                    "then source ${scriptaddr}; fi\0" \
 114         "socfpga_legacy_reset_compat=1\0"
 115
 116 /*
 117  * External memory configurations
 118  */
 119 #define PHYS_SDRAM_1                    0x0
 120 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 121 #define CONFIG_SYS_SDRAM_BASE           0
 122
 123 /*
 124  * Serial / UART configurations
 125  */
 126 #define CONFIG_SYS_NS16550_CLK          100000000
 127 #define CONFIG_SYS_NS16550_MEM32
 128
 129 /*
 130  * Timer & watchdog configurations
 131  */
 132 #define COUNTER_FREQUENCY               400000000
 133
 134 /*
 135  * SDMMC configurations
 136  */
 137 #ifdef CONFIG_CMD_MMC
 138 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 139 #endif
 140 /*
 141  * Flash configurations
 142  */
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 144
 145 /* Ethernet on SoC (EMAC) */
 146 #if defined(CONFIG_CMD_NET)
 147 #define CONFIG_DW_ALTDESCRIPTOR
 148 #endif /* CONFIG_CMD_NET */
 149
 150 /*
 151  * L4 Watchdog
 152  */
 153 #ifndef CONFIG_SPL_BUILD
 154 #undef CONFIG_HW_WATCHDOG
 155 #undef CONFIG_DESIGNWARE_WATCHDOG
 156 #endif
 157 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 158 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 159 #ifndef __ASSEMBLY__
 160 unsigned int cm_get_l4_sys_free_clk_hz(void);
 161 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 162 #endif
 163 #else
 164 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 165 #endif
 166
 167 /*
 168  * SPL memory layout
 169  *
 170  * On chip RAM
 171  * 0xFFE0_0000 ...... Start of OCRAM
 172  * SPL code, rwdata
 173  * empty space
 174  * 0xFFEx_xxxx ...... Top of stack (grows down)
 175  * 0xFFEy_yyyy ...... Global Data
 176  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 177  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 178  * 0xFFE3_FFFF ...... End of OCRAM
 179  *
 180  * SDRAM
 181  * 0x0000_0000 ...... Start of SDRAM_1
 182  * unused / empty space for image loading
 183  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 184  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 185  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 186  *
 187  */
 188 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 189 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 190 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 191 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 192 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 193                                         - CONFIG_SPL_BSS_MAX_SIZE)
 194 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 195 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 196                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 197
 198 /* SPL SDMMC boot support */
 199 #ifdef CONFIG_SPL_LOAD_FIT
 200 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 201 #else
 202 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 203 #endif
 204
 205 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */