include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_s10.h>
  11 #include <asm/arch/handoff_s10.h>
  12
  13 /*
  14  * U-Boot general configurations
  15  */
  16 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_LOADADDR                 0x2000000
  18 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  19 #define CONFIG_REMAKE_ELF
  20 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  21 #define CPU_RELEASE_ADDR                0xFFD12210
  22 #define CONFIG_SYS_CACHELINE_SIZE       64
  23 #define CONFIG_SYS_MEM_RESERVE_SECURE   0       /* using OCRAM, not DDR */
  24
  25 /*
  26  * U-Boot console configurations
  27  */
  28 #define CONFIG_SYS_MAXARGS              64
  29 #define CONFIG_SYS_CBSIZE               2048
  30 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  31                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  32 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  33
  34 /* Extend size of kernel image for uncompression */
  35 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  36
  37 /*
  38  * U-Boot run time memory configurations
  39  */
  40 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  41 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  43                                         + CONFIG_SYS_INIT_RAM_SIZE \
  44                                         - S10_HANDOFF_SIZE)
  45 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  46 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  47
  48 /*
  49  * U-Boot environment configurations
  50  */
  51 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
  52
  53 /*
  54  * QSPI support
  55  */
  56  #ifdef CONFIG_CADENCE_QSPI
  57 /* Enable it if you want to use dual-stacked mode */
  58 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  59
  60 /* Flash device info */
  61
  62 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  63
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_MTD_DEVICE
  66 #define CONFIG_MTD_PARTITIONS
  67 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  68 #endif /* CONFIG_SPL_BUILD */
  69
  70 #ifndef __ASSEMBLY__
  71 unsigned int cm_get_qspi_controller_clk_hz(void);
  72 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  73 #endif
  74
  75 #endif /* CONFIG_CADENCE_QSPI */
  76
  77 /*
  78  * Boot arguments passed to the boot command. The value of
  79  * CONFIG_BOOTARGS goes into the environment value "bootargs".
  80  * Do note the value will override also the chosen node in FDT blob.
  81  */
  82 #define CONFIG_BOOTARGS "earlycon"
  83 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  84                            "run mmcboot"
  85
  86 #define CONFIG_EXTRA_ENV_SETTINGS \
  87         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  88         "bootfile=Image\0" \
  89         "fdt_addr=8000000\0" \
  90         "fdtimage=socfpga_stratix10_socdk.dtb\0" \
  91         "mmcroot=/dev/mmcblk0p2\0" \
  92         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  93                 " root=${mmcroot} rw rootwait;" \
  94                 "booti ${loadaddr} - ${fdt_addr}\0" \
  95         "mmcload=mmc rescan;" \
  96                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  97                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  98         "linux_qspi_enable=if sf probe; then " \
  99                 "echo Enabling QSPI at Linux DTB...;" \
 100                 "fdt addr ${fdt_addr}; fdt resize;" \
 101                 "fdt set /soc/spi@ff8d2000 status okay;" \
 102                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 103                 " ${qspi_clock}; fi; \0" \
 104         "scriptaddr=0x02100000\0" \
 105         "scriptfile=u-boot.scr\0" \
 106         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 107                    "then source ${scriptaddr}; fi\0" \
 108         "socfpga_legacy_reset_compat=1\0"
 109
 110 /*
 111  * Generic Interrupt Controller Definitions
 112  */
 113 #define CONFIG_GICV2
 114
 115 /*
 116  * External memory configurations
 117  */
 118 #define PHYS_SDRAM_1                    0x0
 119 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 120 #define CONFIG_SYS_SDRAM_BASE           0
 121 #define CONFIG_SYS_MEMTEST_START        0
 122 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE - 0x200000
 123
 124 /*
 125  * Serial / UART configurations
 126  */
 127 #define CONFIG_SYS_NS16550_CLK          100000000
 128 #define CONFIG_SYS_NS16550_MEM32
 129
 130 /*
 131  * Timer & watchdog configurations
 132  */
 133 #define COUNTER_FREQUENCY               400000000
 134
 135 /*
 136  * SDMMC configurations
 137  */
 138 #ifdef CONFIG_CMD_MMC
 139 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 140 #endif
 141 /*
 142  * Flash configurations
 143  */
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 145
 146 /* Ethernet on SoC (EMAC) */
 147 #if defined(CONFIG_CMD_NET)
 148 #define CONFIG_DW_ALTDESCRIPTOR
 149 #endif /* CONFIG_CMD_NET */
 150
 151 /*
 152  * L4 Watchdog
 153  */
 154 #ifdef CONFIG_SPL_BUILD
 155 #define CONFIG_HW_WATCHDOG
 156 #define CONFIG_DESIGNWARE_WATCHDOG
 157 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 158 #ifndef __ASSEMBLY__
 159 unsigned int cm_get_l4_sys_free_clk_hz(void);
 160 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 161 #endif
 162 #endif
 163
 164 /*
 165  * SPL memory layout
 166  *
 167  * On chip RAM
 168  * 0xFFE0_0000 ...... Start of OCRAM
 169  * SPL code, rwdata
 170  * empty space
 171  * 0xFFEx_xxxx ...... Top of stack (grows down)
 172  * 0xFFEy_yyyy ...... Global Data
 173  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 174  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 175  * 0xFFE3_FFFF ...... End of OCRAM
 176  *
 177  * SDRAM
 178  * 0x0000_0000 ...... Start of SDRAM_1
 179  * unused / empty space for image loading
 180  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 181  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 182  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 183  *
 184  */
 185 #define CONFIG_SPL_TARGET               "spl/u-boot-spl.hex"
 186 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 187 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 188 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 189 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 190                                         - CONFIG_SPL_BSS_MAX_SIZE)
 191 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 192 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 193                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 194
 195 /* SPL SDMMC boot support */
 196 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 197 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 198
 199 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */