include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_REMAKE_ELF
  19 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  20 #define CPU_RELEASE_ADDR                0xFFD12210
  21
  22 /*
  23  * U-Boot console configurations
  24  */
  25 #define CONFIG_SYS_MAXARGS              64
  26 #define CONFIG_SYS_CBSIZE               2048
  27 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  28                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  29 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  30
  31 /* Extend size of kernel image for uncompression */
  32 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  33
  34 /*
  35  * U-Boot run time memory configurations
  36  */
  37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  41                                         + CONFIG_SYS_INIT_RAM_SIZE \
  42                                         - SOC64_HANDOFF_SIZE)
  43 #else
  44 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  45                                         + 0x100000)
  46 #endif
  47 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  48
  49 /*
  50  * U-Boot environment configurations
  51  */
  52
  53 /*
  54  * QSPI support
  55  */
  56  #ifdef CONFIG_CADENCE_QSPI
  57 /* Enable it if you want to use dual-stacked mode */
  58 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  59
  60 /* Flash device info */
  61
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_MTD_PARTITIONS
  64 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  65 #endif /* CONFIG_SPL_BUILD */
  66
  67 #ifndef __ASSEMBLY__
  68 unsigned int cm_get_qspi_controller_clk_hz(void);
  69 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  70 #endif
  71
  72 #endif /* CONFIG_CADENCE_QSPI */
  73
  74 /*
  75  * Environment variable
  76  */
  77
  78 #ifdef CONFIG_FIT
  79 #define CONFIG_BOOTFILE "kernel.itb"
  80 #else
  81 #define CONFIG_BOOTFILE "Image"
  82 #endif
  83
  84 #define CONFIG_EXTRA_ENV_SETTINGS \
  85         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  86         "bootfile=" CONFIG_BOOTFILE "\0" \
  87         "fdt_addr=8000000\0" \
  88         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  89         "mmcroot=/dev/mmcblk0p2\0" \
  90         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  91                 " root=${mmcroot} rw rootwait;" \
  92                 "booti ${loadaddr} - ${fdt_addr}\0" \
  93         "mmcload=mmc rescan;" \
  94                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  95                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  96         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  97                 " root=${mmcroot} rw rootwait;" \
  98                 "bootm ${loadaddr}\0" \
  99         "mmcfitload=mmc rescan;" \
 100                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 101         "linux_qspi_enable=if sf probe; then " \
 102                 "echo Enabling QSPI at Linux DTB...;" \
 103                 "fdt addr ${fdt_addr}; fdt resize;" \
 104                 "fdt set /soc/spi@ff8d2000 status okay;" \
 105                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 106                 " ${qspi_clock}; fi; \0" \
 107         "scriptaddr=0x02100000\0" \
 108         "scriptfile=u-boot.scr\0" \
 109         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 110                    "then source ${scriptaddr}; fi\0" \
 111         "socfpga_legacy_reset_compat=1\0"
 112
 113 /*
 114  * External memory configurations
 115  */
 116 #define PHYS_SDRAM_1                    0x0
 117 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 118 #define CONFIG_SYS_SDRAM_BASE           0
 119
 120 /*
 121  * Serial / UART configurations
 122  */
 123 #define CONFIG_SYS_NS16550_CLK          100000000
 124 #define CONFIG_SYS_NS16550_MEM32
 125
 126 /*
 127  * Timer & watchdog configurations
 128  */
 129 #define COUNTER_FREQUENCY               400000000
 130
 131 /*
 132  * SDMMC configurations
 133  */
 134 #ifdef CONFIG_CMD_MMC
 135 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 136 #endif
 137 /*
 138  * Flash configurations
 139  */
 140 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 141
 142 /* Ethernet on SoC (EMAC) */
 143 #if defined(CONFIG_CMD_NET)
 144 #define CONFIG_DW_ALTDESCRIPTOR
 145 #endif /* CONFIG_CMD_NET */
 146
 147 /*
 148  * L4 Watchdog
 149  */
 150 #ifndef CONFIG_SPL_BUILD
 151 #undef CONFIG_HW_WATCHDOG
 152 #undef CONFIG_DESIGNWARE_WATCHDOG
 153 #endif
 154 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 155 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 156 #ifndef __ASSEMBLY__
 157 unsigned int cm_get_l4_sys_free_clk_hz(void);
 158 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 159 #endif
 160 #else
 161 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 162 #endif
 163
 164 /*
 165  * SPL memory layout
 166  *
 167  * On chip RAM
 168  * 0xFFE0_0000 ...... Start of OCRAM
 169  * SPL code, rwdata
 170  * empty space
 171  * 0xFFEx_xxxx ...... Top of stack (grows down)
 172  * 0xFFEy_yyyy ...... Global Data
 173  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 174  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 175  * 0xFFE3_FFFF ...... End of OCRAM
 176  *
 177  * SDRAM
 178  * 0x0000_0000 ...... Start of SDRAM_1
 179  * unused / empty space for image loading
 180  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 181  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 182  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 183  *
 184  */
 185 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 186 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 187 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 188 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 189 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 190                                         - CONFIG_SPL_BSS_MAX_SIZE)
 191 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 192 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 193                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 194
 195 /* SPL SDMMC boot support */
 196 #ifdef CONFIG_SPL_LOAD_FIT
 197 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 198 #else
 199 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 200 #endif
 201
 202 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */